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Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation

Published: 05 June 2016 Publication History

Abstract

Verification of modern day electronic circuits has become the bottleneck for the timely delivery of complex SoC designs. We develop a novel cross-layer hardware/software co-simulation framework that can effectively debug and verify an SoC design. We combine high-level C/C++ software with cycle-accurate SystemC hardware, uniquely identify various types of bugs, and help the hardware designer localize them. Experimental results show that we are able to detect and aid in localization of logic bugs from both C/C++ specifications as well as the high-level synthesis engine itself. Our framework is fully automated, representing an important step forward targeting fast and effective SoC design verification.

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    cover image ACM Other conferences
    DAC '16: Proceedings of the 53rd Annual Design Automation Conference
    June 2016
    1048 pages
    ISBN:9781450342360
    DOI:10.1145/2897937
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 05 June 2016

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    Author Tags

    1. SoC design
    2. hardware/software co-simulation
    3. high-level synthesis
    4. verification

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    Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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    • (2024)Advancements in Accelerating Deep Neural Network Inference on AIoT Devices: A SurveyIEEE Transactions on Sustainable Computing10.1109/TSUSC.2024.33531769:6(830-847)Online publication date: Nov-2024
    • (2024)Optimizing Job Offloading Schedule for Collaborative DNN InferenceIEEE Transactions on Mobile Computing10.1109/TMC.2023.327693723:4(3436-3451)Online publication date: Apr-2024
    • (2024)RE-Specter: Examining the Architectural Features of Configurable CNN With Power Side-ChannelIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.339437243:10(2916-2929)Online publication date: Oct-2024
    • (2024)SMOF: Streaming Modern CNNs on FPGAs with Smart Off-Chip Eviction2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM60383.2024.00029(185-196)Online publication date: 5-May-2024
    • (2024)Reliability Modeling of Fault-Tolerant FPGA-Based Architectures in Space Applications for Soft and Hard Error RecoveryIEEE Access10.1109/ACCESS.2024.336958512(31930-31943)Online publication date: 2024
    • (2023)Designing Deep Learning Models on FPGA with Multiple Heterogeneous EnginesACM Transactions on Reconfigurable Technology and Systems10.1145/3615870Online publication date: 10-Oct-2023
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    • (2023)FPGA Implementation of Image Registration Using Accelerated CNN2023 Intelligent Computing and Control for Engineering and Business Systems (ICCEBS)10.1109/ICCEBS58601.2023.10448526(1-7)Online publication date: 14-Dec-2023
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