ABSTRACT
In this paper we propose a high resolution digital calibration method for analog/RF circuits that is an extension of the statistical element selection (SES) approach. As compared to SES, the proposed ESES method provides wider calibration range to accommodate multiple variation sources and produces higher calibration yield for the same calibration resolution target. Two types of ESES-based calibration with application in analog/RF designs are demonstrated; current source calibration and phase/delay calibration. As compared to traditional calibration methods, the proposed ESES-based calibration incurs lower circuit overhead while achieving higher calibration resolution. ESES calibration is further applied to a wideband harmonic-rejection receiver design that achieves best-in-class harmonic-rejection performance after calibration.
- Pelgrom, M. J. M., Tuinhout, H. P., and Vertregt, M., Transistor matching in analog CMOS applications, IEDM, Technical Digest, pp. 915--918, Dec. 1998.Google ScholarCross Ref
- Keskin, G., Proesel, J., and Pileggi, L., Statistical modeling and post manufacturing configuration for scaled analog CMOS, IEEE CICC, pp. 1--4, Sep. 2010.Google ScholarCross Ref
- Liu, R., Pileggi, L., and Weldon, J. A., A Wideband RF receiver with >80 dB harmonic rejection ratio, IEEE CICC, pp. 1--4, Sep. 2014.Google Scholar
- Donovan, C., and Flynn, M., A "Digital" 6-bit ADC in 0.25 um CMOS, IEEE JSSC, vol. 37, no. 3, pp. 432--437, Mar. 2002.Google Scholar
- Liu, R., and Pileggi, L., Low-Overhead Self-Healing Methodology for Current Matching in Current-Steering DAC, IEEE TCAS II, vol. 62, no. 7, pp. 615--655, 2015.Google Scholar
- Vaidyanathan, K., et al,. Exploiting sub-20-nm complementary metal-oxide semiconductor technology challenges to design affordable systems-on-chip, SPIE J. Micro/Nanolithography, MEMS, and MOEMS, vol. 14, no. 1, p. 011007, Jan. 2015.Google ScholarCross Ref
- Tiilikainen, M. P., A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC, IEEE JSSC, pp. 1144--1147, Jul. 2001.Google Scholar
- Bugeja, A. R., and Song, B.-S., A self-trimming 14 b 100 MSample/s CMOS DAC," IEEE ISSCC, pp. 44--45, 2000.Google Scholar
- Schofield, W., et al., A 16b 400MS/s DAC with <-80dBc IMD to 300MHz and <-160dBm/Hz noise power spectral density, IEEE ISSCC, pp. 126--127, 2003.Google Scholar
- Maymandi-Nejad, M., and Sachdev, M., A Monotonic Digitally Controlled Delay Element, IEEE JSSC, vol. 40, no. 11, pp. 2212--2219, Nov. 2005.Google ScholarCross Ref
- Andreani, P., et al., A Digitally Controlled Shunt Capacitor CMOS Delay Line, Analog Circutis and Signal Processing, Kluwer Academic Publishers, vol. 18, pp. 89--96, 1999. Google ScholarDigital Library
- Weldon, J., et al., A 1.75-GHz Highly Integrated Narrow-Band CMOS Transmitter with Harmonic-Rejection Mixers, IEEE JSSC, vol. 36, no. 12, pp. 2003--2015, Dec. 2001.Google Scholar
- Extended statistical element selection: a calibration method for high resolution in analog/RF designs
Recommendations
A wideband RF receiver with extended statistical element selection based harmonic rejection calibration
In this paper we present a wideband harmonic rejection (HR) RF receiver design. Both gain mismatch and phase mismatch of the HR mixer have been calibrated using a design and calibration method called extended statistical element selection to achieve ...
Broadband circularly polarized antenna with moon-shaped parasitic element
A broadband circularly polarized CP circular patch antenna with an L-shaped ground plane and parasitic element is studied. The use of this L-shaped ground is to achieve short probe feed connection to the circular patch, while maintaining a certain ...
On calibration data selection
A stormwater quality model should be calibrated and verified against available data before it can be confidently used. This paper mainly examines two questions: how do the size and selection of calibration data sets affect model performances and how ...
Comments