skip to main content
10.1145/2897937.2898039acmotherconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
research-article

Leveraging FDSOI through body bias domain partitioning and bias search

Published: 05 June 2016 Publication History

Abstract

In FDSOI, sophisticated body biasing schemes can greatly reduce leakage or improve performance as well as efficiency. This paper proposes algorithms to determine body bias domain candidates which then merge those to reach a desired number of domains. Domain candidates are determined using an activation based approach, analyzing mapped verilog netlists to identify which parts of the design are used under specified conditions. Body bias domain partitionings are then determined based on activation and the timing of the partitioned parts. The algorithms include a body bias assignment algorithm to reach given timing goals with multiple domains and cross-domain resource sharing. The approach is compatible with any synthesis optimization and is resource sharing aware. Using an implementation of the proposed algorithms, overall leakage can be significantly reduced in all scenarios while obtaining the same benefits of body biasing. The method is evaluated in STMicro's 28nm FDSOI and Renesas's 65nm SOTB.

References

[1]
J. W. Tschanz, J. T. Kao, S. G. Narendra, R. Nair, D. Antoniadis, A. P. Chandrakasan, V. De et al., "Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage," Solid-State Circuits, IEEE Journal of, vol. 37, no. 11, pp. 1396--1402, 2002.
[2]
R. Teodorescu, J. Nakano, A. Tiwari, and J. Torrellas, "Mitigating parameter variation with dynamic fine-grain body biasing," in Microarchitecture, 2007. MICRO 2007. 40th Annual IEEE/ACM International Symposium on. IEEE, 2007, pp. 27--42.
[3]
D. Lewis, E. Ahmed, D. Cashman, T. Vanderhoek, C. Lane, A. Lee, and P. Pan, "Architectural enhancements in stratix-iii and stratix-iv," in Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays. ACM, 2009, pp. 33--42.
[4]
D. Jacquet, F. Hasbani, P. Flatresse, R. Wilson, F. Arnaud, G. Cesana, T. Di Gilio, C. Lecocq, T. Roy, A. Chhabra et al., "A 3 ghz dual core processor arm cortex tm-a9 in 28 nm utbb fd-soi cmos with ultra-wide voltage range and energy efficiency optimization," Solid-State Circuits, IEEE Journal of, vol. 49, no. 4, pp. 812--826, 2014.
[5]
Y. Akgul, D. Puschini, S. Lesecq, E. Beigné, I. Miro-Panades, P. Benoit, and L. Torres, "Power management through dvfs and dynamic body biasing in fd-soi circuits," in Proceedings of the 51st Annual Design Automation Conference. ACM, 2014, pp. 1--6.
[6]
H. Okuhara, K. Kitamori, Y. Fujita, K. Usami, and H. Amano, "An optimal power supply and body bias voltage for an ultra low power micro-controller with silicon on thin box mosfet," in Proceedings of International Symposium on Low Power Electronics and Design (ISLPED). IEEE, 2015.
[7]
M. Hioki, T. Sekigawa, T. Nakagawa, H. Koike, Y. Matsumoto, T. Kawanami, and T. Tsutsumi, "Fully-functional fpga prototype with fine-grain programmable body biasing," in Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays. ACM, 2013, pp. 73--80.
[8]
J. M. Kühn, D. Peterson, H. Amano, O. Bringmann, and W. Rosenstiel, "Spatial and temporal granularity limits of body biasing in utbb-fdsoi," in Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition. EDA Consortium, 2015.
[9]
A. Dobriyal, R. Gonnabattula, P. Dasgupta, and C. R. Mandal, "Workload driven power domain partitioning," in Proceedings of the 16th international conference on Progress in VLSI Design and Test. Springer-Verlag, 2012, pp. 147--155.

Cited By

View all
  • (2020)Heuristic Methods for Fine-Grain Exploitation of FDSOIIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.293505339:10(2860-2871)Online publication date: Oct-2020
  • (2018)Optimization of Body Biasing for Variable Pipelined Coarse-Grained Reconfigurable ArchitecturesIEICE Transactions on Information and Systems10.1587/transinf.2017EDP7308E101.D:6(1532-1540)Online publication date: 1-Jun-2018
  • (2017)Body bias optimization for variable pipelined CGRA2017 27th International Conference on Field Programmable Logic and Applications (FPL)10.23919/FPL.2017.8056851(1-4)Online publication date: Sep-2017
  • Show More Cited By

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Other conferences
DAC '16: Proceedings of the 53rd Annual Design Automation Conference
June 2016
1048 pages
ISBN:9781450342360
DOI:10.1145/2897937
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 June 2016

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. FDSOI
  2. body biasing
  3. domain partitioning
  4. leakage optimization

Qualifiers

  • Research-article

Conference

DAC '16

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)6
  • Downloads (Last 6 weeks)0
Reflects downloads up to 08 Feb 2025

Other Metrics

Citations

Cited By

View all
  • (2020)Heuristic Methods for Fine-Grain Exploitation of FDSOIIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.293505339:10(2860-2871)Online publication date: Oct-2020
  • (2018)Optimization of Body Biasing for Variable Pipelined Coarse-Grained Reconfigurable ArchitecturesIEICE Transactions on Information and Systems10.1587/transinf.2017EDP7308E101.D:6(1532-1540)Online publication date: 1-Jun-2018
  • (2017)Body bias optimization for variable pipelined CGRA2017 27th International Conference on Field Programmable Logic and Applications (FPL)10.23919/FPL.2017.8056851(1-4)Online publication date: Sep-2017
  • (2017)Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable AcceleratorIEICE Transactions on Information and Systems10.1587/transinf.2017PAP0013E100.D:12(2828-2836)Online publication date: 2017
  • (2017)Break even time analysis using empirical overhead parameters for embedded systems on SOTB technology2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS)10.1109/DCIS.2017.8311633(1-6)Online publication date: Nov-2017

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media