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StitchUp: automatic control flow protection for high level synthesis circuits

Published: 05 June 2016 Publication History

Abstract

Soft-error detection in FPGAs typically requires replication, doubling the required area. We propose an approach which distinguishes between tolerable errors in data-flow, such-as arithmetic, and intolerable errors in control-flow, such as branches and their data-dependencies. This approach is demonstrated in a new high-level synthesis compiler pass called StitchUp, which precisely identifies the control critical parts of the design, then automatically replicates only that part. We applied StitchUp to the CHStone benchmark suite and performed exhaustive hardware fault injection in each case, finding that all control-flow errors were detected while only requiring 1% circuit area overhead in the best case.

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  • (2023)Criticality-Aware Negotiation-Driven Scrubbing Scheduling for Reliability Maximization in SRAM-Based FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.325771042:11(3881-3894)Online publication date: Nov-2023
  • (2023)On the Prediction of Hardware Security Properties of HLS Designs Using Graph Neural Networks2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)10.1109/DFT59622.2023.10313544(1-6)Online publication date: 3-Oct-2023
  • (2020)Light-Weight Soft-Errors Detection Mechanism in High-Level Synthesis2020 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS45731.2020.9180591(1-5)Online publication date: Oct-2020
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  1. StitchUp: automatic control flow protection for high level synthesis circuits

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    cover image ACM Other conferences
    DAC '16: Proceedings of the 53rd Annual Design Automation Conference
    June 2016
    1048 pages
    ISBN:9781450342360
    DOI:10.1145/2897937
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 05 June 2016

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    • (2023)Criticality-Aware Negotiation-Driven Scrubbing Scheduling for Reliability Maximization in SRAM-Based FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.325771042:11(3881-3894)Online publication date: Nov-2023
    • (2023)On the Prediction of Hardware Security Properties of HLS Designs Using Graph Neural Networks2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)10.1109/DFT59622.2023.10313544(1-6)Online publication date: 3-Oct-2023
    • (2020)Light-Weight Soft-Errors Detection Mechanism in High-Level Synthesis2020 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS45731.2020.9180591(1-5)Online publication date: Oct-2020
    • (2019)Exploring Design Trade-offs in Fault-Tolerant Behavioral Hardware AcceleratorsProceedings of the 2019 Great Lakes Symposium on VLSI10.1145/3299874.3318020(291-294)Online publication date: 13-May-2019
    • (2018)Injecting FPGA Configuration Faults in Parallel2018 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2018.00037(198-205)Online publication date: Dec-2018
    • (2017)HLshield: a reliability enhancement framework for high-level synthesis2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)10.1109/SIES.2017.7993378(1-10)Online publication date: Jun-2017
    • (2017)Vulnerability analysis of storage elements in HLS-generated designs using high-level profiling2017 2nd International Conference on System Reliability and Safety (ICSRS)10.1109/ICSRS.2017.8272819(190-194)Online publication date: Dec-2017
    • (2017)TLegUp: A TMR Code Generation Tool for SRAM-Based FPGA Applications Using HLS2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM.2017.57(129-132)Online publication date: Apr-2017
    • (2017)Using Runahead Execution to Hide Memory Latency in High Level Synthesis2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM.2017.33(109-116)Online publication date: Apr-2017

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