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Write-back aware shared last-level cache management for hybrid main memory

Published: 05 June 2016 Publication History

Abstract

Hybrid main memory with both DRAM and emerging non-volatile memory (NVM) becomes a promising solution for high performance and energy-efficient embedded systems. Cache plays an important role and highly affects the number of write backs to NVM and DRAM blocks. However, existing cache policies fail to fully address the significant asymmetry between NVM operations (especially writes) and DRAM operations, leading to non-optimal system designs. We propose a write-back aware last-level cache management scheme for the hybrid main memory, which improves the cache hit ratio of NVM memory blocks and minimizes write-backs to NVM. Experimental results show that our proposed framework leads to better performance and energy saving compared with the state-of-the-art cache management scheme for hybrid main memory architecture.

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  • (2021)SeNonDiv: Securing Non-Volatile Memory using Hybrid Memory and Critical Data Diversion2021 22nd International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED51717.2021.9424292(522-528)Online publication date: 7-Apr-2021
  • (2020)Crab-treeACM Transactions on Embedded Computing Systems10.1145/339623619:5(1-26)Online publication date: 26-Sep-2020
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  1. Write-back aware shared last-level cache management for hybrid main memory

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    cover image ACM Other conferences
    DAC '16: Proceedings of the 53rd Annual Design Automation Conference
    June 2016
    1048 pages
    ISBN:9781450342360
    DOI:10.1145/2897937
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 05 June 2016

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    View all
    • (2024)MORSE: Memory Overwrite Time Guided Soft Writes to Improve ReRAM Energy and EnduranceProceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques10.1145/3656019.3676890(26-39)Online publication date: 14-Oct-2024
    • (2021)SeNonDiv: Securing Non-Volatile Memory using Hybrid Memory and Critical Data Diversion2021 22nd International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED51717.2021.9424292(522-528)Online publication date: 7-Apr-2021
    • (2020)Crab-treeACM Transactions on Embedded Computing Systems10.1145/339623619:5(1-26)Online publication date: 26-Sep-2020
    • (2020)Reuse Distance-based Victim Cache for Effective Utilisation of Hybrid Main Memory SystemACM Transactions on Design Automation of Electronic Systems10.1145/338073225:3(1-32)Online publication date: 28-Feb-2020
    • (2019)Crash recoverable ARMv8-oriented B+-tree for byte-addressable persistent memoryProceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems10.1145/3316482.3326358(33-44)Online publication date: 23-Jun-2019
    • (2019)Writeback-Aware LLC Management for PCM-Based Main Memory SystemsACM Transactions on Design Automation of Electronic Systems10.1145/329200924:2(1-19)Online publication date: 10-Jan-2019
    • (2019)Reducing Writebacks Through In-Cache DisplacementACM Transactions on Design Automation of Electronic Systems10.1145/328918724:2(1-21)Online publication date: 10-Jan-2019
    • (2019)Bandwidth-Aware Last-Level Caching: Efficiently Coordinating Off-Chip Read and Write Bandwidth2019 IEEE 37th International Conference on Computer Design (ICCD)10.1109/ICCD46524.2019.00022(109-118)Online publication date: Nov-2019
    • (2018)WALL: A writeback-aware LLC management for PCM-based main memory systems2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2018.8342051(449-454)Online publication date: Mar-2018
    • (2018)Shared Last-Level Cache Management and Memory Scheduling for GPGPUs with Hybrid Main MemoryACM Transactions on Embedded Computing Systems10.1145/323064317:4(1-25)Online publication date: 31-Jul-2018
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