Bo Yuan
ABSTRACT
Discrete Fourier Transformation (DFT)/Fast Fourier Transformation (FFT) are the widely used techniques in numerous modern signal processing applications. In general, because of their inherent multiplication-intensive characteristics, the hardware implementations of DFT/FFT usually require a large amount of hardware resource, which limits their applications in area-constraint scenarios. To overcome this challenge, this paper, for the first time, proposes area-efficient error-resilient DFT designs using stochastic computing. By leveraging low-complexity stochastic multipliers, two types of stochastic DFT design are presented with significant reduction in overall area. Analysis results show that compared with the conventional design, the proposed two 256-point stochastic DFT designs achieve 76% and 62% reduction in area, respectively. More importantly, these stochastic DFT designs also show much stronger error-resilience, which is very attractive in nanoscale CMOS era.
- K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, New York, NY: John Wiley & Sons Inc., 1999.Google Scholar
- M. Ayinala and K.K. Parhi, "FFT Architectures for Real-valued Signals based on Radix-23 and Radix-24 algorithms," IEEE Trans. Circuits and Systems-I: Regular Papers, 60(9), pp. 2422--2430, Sept. 2013Google ScholarCross Ref
- M. Ayinala, M.J. Brown and K.K. Parhi, "Pipelined Parallel FFT Architectures via Folding Transformation," IEEE Trans. VLSI Systems, pp. 1068--1081, 20(6), June 2012 Google ScholarDigital Library
- C. Cheng and K.K. Parhi, "Hardware Efficient Fast Computation of the Discrete Fourier Transform," Springer Journal of VLSI Signal Processing, pp. 159--171, 42(2), Feb. 2006 Google ScholarDigital Library
- B. Gaines, "Stochastic computing systems," Advances in Information Systems Science, vol. 2, no. 2, pp. 37--172, 1969.Google ScholarCross Ref
- B. Brown and H. Card, "Stochastic neural computation I: computational elements," IEEE Trans. Comput., vol. 50, no. 9, pp. 891--905, Sept. 2001. Google ScholarDigital Library
- Oppenheim, A. V. and Schafer, R. W. Discrete-Time Signal Processing. Prentice-Hall, Englewood Cliffs, NJ, 1989. Google ScholarDigital Library
- B. Yuan, C. Zhang and Z. Wang, "Design space exploration for Hardware-efficient stochastic computing: A case study on discrete cosine transformation," accepted by IEEE Intl. Conf. on Acoustics, Speech and Signal Processing (ICASSP) 2016Google Scholar
- Y-N. Chang and K. K. Parhi, "Architectures for digital filters using stochastic computing," in Proc. of 2013 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP),pp. 2697--2701, 2013.Google Scholar
- A. Alaghi, Cheng Li and John P. Hayes. "Stochastic circuits for real-time image processing applications," in Proc. of Design Automation Conference (DAC), pp. 1--6, 2013. Google ScholarDigital Library
- A. Alaghi and J. P. Hayes, "Fast and accurate computation using stochastic circuits," in Proc. of Design, Automation and Test Conference in Europe (DATE), pp. 1--4, 2014. Google ScholarDigital Library
- P. Li, D. J. Lilja, W. Qian, and K. Bazargan, "Computation on stochastic bit streams: Digital image processing case studies," IEEE Trans. on Very Large Scale Integrated (VLSI) Systems, vol. 22, no. 3, pp. 449--462, April 2013. Google ScholarDigital Library
- W. Qian, X. Li, Marc D. Riedel, K. Bazargan, and D. J. Lilja, "An architecture for fault-tolerant computation with stochastic logic," IEEE Trans. on Computers, vol. 60, no. 1, pp. 93--105, 2011. Google ScholarDigital Library
- S. Sharifi Tehrani, W. Gross and S. Mannor, "Stochastic decoding of LDPC codes," IEEE Commun. Lett., vol. 10, no. 10, pp. 716--718, Oct. 2006.Google ScholarCross Ref
- S. Sharifi Tehrani, S. Mannor, and W. J. Gross, "Fully parallel stochastic LDPC decoders," IEEE Trans. on Signal Processing, vol. 56, no. 11, pp. 5692--5703, Nov.2008. Google ScholarDigital Library
- T-H. Chen and J.P. Hayes, "Design of Stochastic Viterbi Decoders for Convolutional Codes," in Proc. of IEEE Intl. Design and Diagnostics of Electronic Circuits. & Systems. (DDECS), pp. 66--71, April 2013.Google Scholar
- X-R Lee, C-L Chen, H-C Chang and C-Y Lee, "Stochastic decoding for LDPC convolutional codes," in Proc. IEEE Int. Symp. Circuits Syst.(ISCAS), pp. 2621--2624, May 2012.Google Scholar
- A. Naderi, S. Mannor, M. Sawan and W. J. Gross, "Delayed stochastic decoding of LDPC Codes," IEEE Trans.on Signal Processing, vol. 59, no. 11, pp. 5617--5626, Nov. 2011. Google ScholarDigital Library
- X. R. Lee, C. L. Chen, H. C. Chang and C. Y. Lee, "A 7.92 Gb/s 437.2 mW stochastic LDPC decoder chip for IEEE 802.15.3C applications," IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 62, no. 2, Feb. 2015.Google ScholarCross Ref
- B. Yuan and K.K. Parhi, "Successive Cancellation Decoding of Polar Codes Using Stochastic Computing," in Proc. of 2015 IEEE International Symposium on Circuits and Systems (ISCAS), May 2015.Google Scholar
Index Terms
- Area-Efficient Error-Resilient Discrete Fourier Transformation Design using Stochastic Computing
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