Poorna Marthi
ABSTRACT
In this paper, study of different digital logic circuits developed using two-BDT ballistic nanostructure is presented. New D flip-flop (DFF) based on the same nanostructure is also proposed. The logic structure comprises two ballistic deflection transistors (BDTs) that are experimentally proven to operate at Terahertz frequencies. The non-linear behavior of the BDT's transfer characteristic has been perfectly reproduced by means of Monte Carlo simulations, where a specific attention has been devoted to surface charges. An analytical model built on the results of advanced MC simulations has been integrated into a behavioral Verilog AMS module to confirm the functionality of the circuit design. The module is used to analyze operating conditions of different combinational circuits and to investigate the feasibility of DFF design using BDT nanostructure. The simulation results indicate successful operation of both combinational and sequential circuits developed using two-BDT logic structure under proper biasing of gate and source terminals. The operating voltages of the proposed DFF are estimated to be + 225mV.
- Diduck, Q., Margala, M., Feldman, M., 2006. A TeraHertz Transistor Based on Geometrical Deflection of Ballistic Current. Microwave Symposium Digest IEEE MTT-S International, pp. 345--347. DOI = http://dx.doi.org/10.1109/MWSYM.2006.249522Google Scholar
Cross Ref
- Wolpert, D., Irie. H., Sobolweski, R., Ampadu, P., Diduck, Q., and Margala, M. 2009. Ballistic deflection transistors and emerging nanoscale era. in Proc. ISCAS, May 27, pp. 61--64. DOI = http://dx.doi.org/10.1109/ISCAS.2009.5117685Google Scholar
- Kaushal, V., Yu, Q., Ampadu, P., Guarino, G., and Sobolweski, R, and Margala, M. 2010. A study of Geometry effects on the performance of ballistic deflection transistor. IEEE Trans. Nanotechnol., Vol.9, no. 6, pp. 723--733, November. DOI = http://dx.doi.org/10.1109/TNANO.2010.2050069 Google ScholarDigital Library
- Kaushal, V., Margala, M., Yu, Q., Ampadu, P., Guarino, G., and Sobolweski, R.2009. Current Transport modeling and experimental study of THz room temperature ballistic deflection transistors, J. Phs., Conf. ser., vol. 193, pp. 012092--1-012092--4. DOI = http://dx.doi.org/10.1088/1742--6596/193/1/012092Google Scholar
- Kaushal, V., Diduck, Q., Margala, M. 2009. Study of Leakage Current Mechanisms in ballistic deflection transistors. Proc. of ACM 19th Great Lakes Symposium on VLSI. (GLSVLSI 2009). pp 165--168. DOI = http://dx.doi.org/10.1145/1531542.1531584 Google ScholarDigital Library
- Torre, I., Mateos, J., Gonzalez, T., Kaushal, V., and Margala, M. 2013. Ballistic Deflection Transistors : geometry dependence and Boolean operations. 2013 Spanish Conference on Electron Devices (CDE), pp. 187--190. DOI = http://dx.doi.org/10.1109/CDE.2013.6481374Google ScholarCross Ref
- Wolpert, D., Diduck, Q.,and Ampadu, P.2011. NAND gate Design for Ballistic Deflection Transistors. IEEE Trans. Nanotechnol., Vol. 10, no. 1, pp.150--154, Jan.2 DOI = http://dx.doi.org/10.1109/TNANO.2009.2034962 Google ScholarDigital Library
- Wolpert, D., Torre, I., Kaushal, V., Margala, M., Ampadu, P., General purpose logic gate using ballistic nanotransistors. 2011 IEEE Conference on Nanotechnology (IEEE-Nano), pp. 1171--1176. DOI = http://dx.doi.org/10.1109/NANO.2011.6144451Google ScholarCross Ref
- Mateos. J, Vasallo. B.G., Pardo, D., Gonzalez, T., Galloo, J.S., Roelens, Y., Bollaert, S., and Cappy.A. 2003. Ballistic Nanodevices for TeraHertz data processing : Monte Carlo Simulations. Nanotechnology, vol. 14, pp. 117--122. DOI = http://dx.doi.org/10.1088/0957--4484/14/2/303.Google ScholarCross Ref
- Millithaler, J.F, Iñiguez-de-la-Torre, I., Mateos, J., Gonzalez T, Margala, M., 2015. Study of surface charges in ballistic deflection transistors. IOP Nanotechnology, DOI = http://dx.doi.org/10.1088/0957--4484/26/48/485202.Google Scholar
- Torre, I., Purohit, S., Kaushal, V., Margala, M., Gong, M., Sobolweski, R., Wolpert, D., Ampadu, P., Gonzalez, T., and Mateos. J.2011. Exploring Digital Logic Design using Ballistic Deflection Transistors through Monte Carlo simulations. IEEE Transactions on Nanotechnology, Vol. 10, No. 6, November. DOI =http://dx.doi.org/10.1109/TNANO.2011.2142321 Google ScholarDigital Library
- Marthi, P., Millithaler, J.F, Iñiguez-de-la-Torre, I., Mateos, J., Gonzalez T, Margala, M., 2015, "Exploration of digital latch design using ballistic deflection transistors- modeling and simulation", NMDC 2015.Google ScholarCross Ref
- Marthi, P., Hossain, N., Millithaler, J.F, Margala, M., A New Level Sensitive D Latch using Ballistic Nanodevices, ISCAS, May, 2016.Google Scholar
Index Terms
- Modeling and Study of Two-BDT-Nanostructure based Sequential Logic Circuits
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