short-paper

Modular Placement for Interposer based Multi-FPGA Systems

Authors:

Yuchun MaAuthors Info & Claims

GLSVLSI '16: Proceedings of the 26th edition on Great Lakes Symposium on VLSI

Pages 93 - 98

https://doi.org/10.1145/2902961.2903025

Published: 18 May 2016 Publication History

Abstract

Novel device with multiple FPGAs on-chip based on interposer interconnection has emerged to resolve the IOs limit and improve the inter-FPGA communication delay. However, new challenges arise for the placement on such architecture. Firstly, existing work does not consider the detailed models for the path wirelength and delay estimation for interposer, which may significantly affect the placement quality. Secondly, previous work is mostly based on traditional tile-based placement which is slow for the placement of large design on multiple FPGAs.

In this paper, we propose a new fast two-stage modular placement flow for interposer based multiple FPGAs aiming for delay optimization with the incorporation of a detailed interposer routing model for wirelength and delay estimation. Firstly, we adopt the force-directed method for its global property to get an efficient solution as a start point of the placement. Secondly, we adopt the simulated annealing (SA) for its efficiency and effectiveness in searching the refinement solution. In order to speed up the refinement, the hierarchical B*-tree (HB*-tree) is employed to enable a fast search and convergence. The experiments demonstrate that our flow can achieve an efficient solution in a comparable time. The proposed approach is scalable to different design size.

References

[1]

C. Ababei. Tpr: Three-d place and route for fpgas. In FPL. 2004.

[2]

S. Areibi and etc. Hierarchical fpga placement. CJECE, 2007.

[3]

P. Banerjee and etc. Floorplanning for Partially Reconfigurable FPGAs. TCAD, 2011.

Digital Library

[4]

J. Barnes. and P. Hut. A hierarchical $o(nlog^n)$ force calculattion algorithm. Nature, 1986.

[5]

T. Chen and Y. Chang. Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing. TCAD, 2006.

Digital Library

[6]

J. Cong and G. Luo. An analytical placer for mixed-size 3d placement. In ISPD, 2010.

Digital Library

[7]

W. Donath. Complexity theory and design automation. In DAC, 1980.

Digital Library

[8]

K. Eguro and S. Hauck. Enhancing timing-driven fpga placement for pipelined netlists. In DAC, 2008.

Digital Library

[9]

A. Hahn Pereira and V. Betz. Cad and routing architecture for interposer-based multi-fpga systems. In FPGA, 2014.

Digital Library

[10]

Y.-K. Ho and Y.-W. Chang. Multiple chip planning for chip-interposer codesign. In DAC, 2013.

Digital Library

[11]

G. Karypis and etc. Multilevel hypergraph partitioning: Application in vlsi domain. In DAC, 1997.

Digital Library

[12]

C. Kim and etc. Performance-driven circuit partitioning for prototyping by using multiple fpga chips. In ASP-DAC, 1995.

Digital Library

[13]

S.-J. Lee and K. Raahemifar. Fpga placement optimization methodology survey. In CCECE, 2008.

[14]

Q. Liu and etc. Ralp: Reconvergence-aware layer partitioning for 3d fpgas. In ReConFig, 2013.

[15]

W.-H. Liu, M.-S. Chang, and T.-C. Wang. Floorplanning and signal assignment for silicon interposer-based 3d ics. In DAC, 2014.

Digital Library

[16]

G. Marcel and A. Jason. Design Re-use for Compile Time Reduction in FPGA High-level Synthesis Flows. In FPT, 2014.

[17]

F. Mo, A. Tabbara, and R. Brayton. A force-directed macro-cell placer. In ICCAD, 2000.

Digital Library

[18]

H. Murata and etc. Rectangle-packing-based module placement. In ICCAD, 1995.

Digital Library

[19]

J. Rose and et al. The VTR Project: Architecture and CAD for FPGAs from Verilog to Routing. In FPGA, 2012.

Digital Library

[20]

K. Roy-Neogi and C. Sechen. Multiple fpga partitioning with performance optimization. In FPGA, 1995.

Digital Library

[21]

D. Seemuth and etc. Automatic die placement and flexible i/o assignment in 2.5d ic design. In ISQED, 2015.

[22]

M. Shih and etc. Performance-driven system partitioning on multi-chip modules. In DAC, 1992.

Digital Library

[23]

K. Siozios and D. Soudris. A tabu-based partitioning and layer assignment algorithm for 3-d fpgas. Embedded Systems Letters, IEEE, 2011.

Digital Library

[24]

T.-C. Wang and D. Wong. An Optimal Algorithm for Floorplan Area Optimization. In DAC, 1991.

Digital Library

[25]

N.-S. Woo and J. Kim. An efficient method of partitioning circuits for multiple-fpga implementation. In DAC, 1993.

Digital Library

[26]

Xilinx. Partial Reconfiguration of Xilinx FPGAs Using ISE Design Suite, 2012.

[27]

Xilinx. White Paper: Vivado Design Suite, 2012.

[28]

Xilinx. 7 Series FPGA Overview, 2013.

[29]

M. Xu and etc. Near-linear wirelength estimation for fpga placement. In CCECE, 2009.

[30]

P. Zhou and etc. 3d-staf: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. In ICCAD, 2007.

Digital Library

Cited By

Raikar RStroobandt D(2024)LiquidMD: Optimizing Inter-die and Intra-die placement for 2.5D FPGA ArchitecturesProceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies10.1145/3665283.3665295(90-98)Online publication date: 19-Jun-2024
https://dl.acm.org/doi/10.1145/3665283.3665295
Di ZTao RMai JChen LLin Y(2024)LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line MinimizationIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2023.334055471:3(1259-1272)Online publication date: Mar-2024
https://doi.org/10.1109/TCSI.2023.3340554
Raikar RStroobandt D(2023)Modularity Driven Parallel Placement Algorithm for 2.5D FPGA ArchitecturesProceedings of the 2023 ACM International Workshop on System-Level Interconnect Pathfinding10.1145/3632409.3632839(1-8)Online publication date: 2-Nov-2023
https://dl.acm.org/doi/10.1145/3632409.3632839
Show More Cited By

Index Terms

Modular Placement for Interposer based Multi-FPGA Systems
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement

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Published In

cover image ACM Conferences

GLSVLSI '16: Proceedings of the 26th edition on Great Lakes Symposium on VLSI

May 2016

462 pages

ISBN:9781450342742

DOI:10.1145/2902961

General Chairs:
Ayse K. Coskun
Boston University, USA
,
Martin Margala
University of Massachusetts, Lowell, USA
,
Program Chairs:
Laleh Behjat
University of Calgary, Canada
,
Jie Han
University of Alberta, Canada

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation
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Association for Computing Machinery

New York, NY, United States

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Published: 18 May 2016

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Ministry of Education
Hong Kong SAR.

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GLSVLSI '16

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SIGDA

GLSVLSI '16: Great Lakes Symposium on VLSI 2016

May 18 - 20, 2016

Massachusetts, Boston, USA

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GLSVLSI '16 Paper Acceptance Rate 50 of 197 submissions, 25%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Great Lakes Symposium on VLSI 2025

June 30 - July 2, 2025

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Citations

Cited By

Raikar RStroobandt D(2024)LiquidMD: Optimizing Inter-die and Intra-die placement for 2.5D FPGA ArchitecturesProceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies10.1145/3665283.3665295(90-98)Online publication date: 19-Jun-2024
https://dl.acm.org/doi/10.1145/3665283.3665295
Di ZTao RMai JChen LLin Y(2024)LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line MinimizationIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2023.334055471:3(1259-1272)Online publication date: Mar-2024
https://doi.org/10.1109/TCSI.2023.3340554
Raikar RStroobandt D(2023)Modularity Driven Parallel Placement Algorithm for 2.5D FPGA ArchitecturesProceedings of the 2023 ACM International Workshop on System-Level Interconnect Pathfinding10.1145/3632409.3632839(1-8)Online publication date: 2-Nov-2023
https://dl.acm.org/doi/10.1145/3632409.3632839
Du LLiang TSinha SXie ZZhang WIenne PZhang Z(2023)FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAsProceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays10.1145/3543622.3573188(15-25)Online publication date: 12-Feb-2023
https://dl.acm.org/doi/10.1145/3543622.3573188
Nayak BRay B(2023)ISP: An Improved Slicing Pair Code for Skewed Slicing Floorplan2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID)10.1109/VLSID57277.2023.00051(205-210)Online publication date: Jan-2023
https://doi.org/10.1109/VLSID57277.2023.00051
Lin JTsai TTsai T(2023)Multilevel Fixed-Outline Component Placement and Graph-Based Ball Assignment for System in PackageIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.329138131:9(1308-1319)Online publication date: Sep-2023
https://doi.org/10.1109/TVLSI.2023.3291381
Alonso TPetrica LRuiz MPetri-Koenig JUmuroglu YStamelos IKoromilas EBlott MVissers K(2021)Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic PartitioningACM Transactions on Reconfigurable Technology and Systems10.1145/347056715:2(1-34)Online publication date: 6-Dec-2021
https://dl.acm.org/doi/10.1145/3470567
Guo LChi YWang JLau JQiao WUstun EZhang ZCong JShannon LAdler M(2021)AutoBridgeThe 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3431920.3439289(81-92)Online publication date: 17-Feb-2021
https://dl.acm.org/doi/10.1145/3431920.3439289
Yan J(2021)Via-Avoidance-Oriented Interposer Routing for Layer Minimization in 2.5-D IC DesignsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.311391829:11(1889-1902)Online publication date: Nov-2021
https://doi.org/10.1109/TVLSI.2021.3113918
Voss NQuintana PMencer OLuk WGaydadjiev G(2019)Memory Mapping for Multi-die FPGAs2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM.2019.00021(78-86)Online publication date: Apr-2019
https://doi.org/10.1109/FCCM.2019.00021
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