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Dynamic Real-Time Scheduler for Large-Scale MPSoCs

Published: 18 May 2016 Publication History

Abstract

Large-scale MPSoCs requires a scalable and dynamic real-time (RT) task scheduler, able to handle non-deterministic computational behaviors. Current proposals for MPSoCs have limitations, as lack of scalability, complex static steps, validation with abstract models, or are not flexible to enable changes at runtime of the RT constraints. This work proposes a hierarchical task scheduler with monitoring features. The scheduler is dynamic, supporting changes in RT constraints at runtime. An API enables these features allowing to the application developer to reconfigure the tasks' period, deadline, and execution time by annotating the task code. At runtime, according to the task execution, the scheduler handles the API calls and adjust itself to ensure RT guarantees according to the new constraints. Scalability is ensured by dividing the scheduler into two hierarchical levels: LS (Local Schedulers), and CS (Cluster Schedulers). The LS runs at the processor level, using the LST (Least Slack-Time) algorithm. The CS runs at the cluster level, i.e., a group of processors controlled by a manager processor. The CS receives messages from the LSs, informing the processor slack-time, deadline violations, and RT changes. The CS implements an RT adaptation heuristic, triggering task migrations according to RT reconfiguration or deadline misses. Results show a negligible overhead in the applications' execution time and the fulfillment of the applications' RT constraints even with a high degree of resources sharing, in both processors and NoC.

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Cited By

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  • (2019)Development of a Random Test Generator for Multi-Core Processor Design Verification2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA)10.1109/ICECA.2019.8822103(1200-1204)Online publication date: Jun-2019
  • (2019)Memphis: a framework for heterogeneous many-core SoCs generation and validationDesign Automation for Embedded Systems10.1007/s10617-019-09223-423:3-4(103-122)Online publication date: 20-Aug-2019
  • (2017)SDN-Based Circuit-Switching for Many-Cores2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2017.74(385-390)Online publication date: Jul-2017
  • Show More Cited By

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cover image ACM Conferences
GLSVLSI '16: Proceedings of the 26th edition on Great Lakes Symposium on VLSI
May 2016
462 pages
ISBN:9781450342742
DOI:10.1145/2902961
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 18 May 2016

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Author Tags

  1. mpsoc
  2. real-time
  3. runtime
  4. scheduler
  5. slack-time

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GLSVLSI '16
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GLSVLSI '16: Great Lakes Symposium on VLSI 2016
May 18 - 20, 2016
Massachusetts, Boston, USA

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GLSVLSI '16 Paper Acceptance Rate 50 of 197 submissions, 25%;
Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

View all
  • (2019)Development of a Random Test Generator for Multi-Core Processor Design Verification2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA)10.1109/ICECA.2019.8822103(1200-1204)Online publication date: Jun-2019
  • (2019)Memphis: a framework for heterogeneous many-core SoCs generation and validationDesign Automation for Embedded Systems10.1007/s10617-019-09223-423:3-4(103-122)Online publication date: 20-Aug-2019
  • (2017)SDN-Based Circuit-Switching for Many-Cores2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2017.74(385-390)Online publication date: Jul-2017

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