research-article

Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM

Authors:

Swarup BhuniaAuthors Info & Claims

GLSVLSI '16: Proceedings of the 26th edition on Great Lakes Symposium on VLSI

Pages 299 - 304

https://doi.org/10.1145/2902961.2903042

Published: 18 May 2016 Publication History

Abstract

Inherent stochastic physical mechanisms in emerging nonvolatile memories (NVMs), such as resistive random-access-memory (RRAM), have recently been explored for hardware security applications. Unlike the conventional silicon Physical Unclonable Functions (PUFs) that are solely based on manufacturing process variation, RRAM has some intrinsic randomness in its physical mechanisms that can be utilized as entropy sources; for instance, resistance variation, random telegraph noise, and probabilistic switching behaviors. This paper reviews the challenges and opportunities in building security primitives with emerging devices. In particular, it presents research progress of RRAM-based hardware security primitives, including PUF and True Random Number Generator (TRNG).

References

[1]

G. E. Suh, S. Devadas, "Physical unclonable functions for device authentication and secret key generation," in ACM Design Automation Conference, 2007.

Digital Library

[2]

H.-S. P. Wong, S. Raoux, S. Kim, J. Liang, J. P. Reifenberg, B. Rajendran, M. Asheghi, and K. E. Goodson, "Phase change memory," Proceedings of the IEEE, vol. 98, no. 12, p. 2201--2227, 2010.

[3]

B. J. Zhu, "Magnetoresistive random access memory: the path to competitiveness and scalability," Proceedings of the IEEE, vol. 96, no. 11, p. 1786--1798, 2008.

[4]

H.-S. P. Wong, H.-Y. Lee, S. Yu, Y.-S. Chen, Y. Wu, P.-S. Chen, B. Lee, F. T. Chen, and M.-J. Tsai, "Metal-oxide RRAM," Proceedings of the IEEE, vol. 100, no. 6, p. 1951--1970, 2012.

[5]

S.-S. Sheu, M.-F. Chang, K.-F. Lin, C.-W. Wu, Y.-S. Chen, P.-F. Chiu, C.-C. Kuo, Y.-S. Yang, P.-C. Chiang, W.-P. Lin, C.-H. Lin, H.-Y. Lee, P.-Y. Gu, S.-M. Wang, F. T. Chen, K.-L. Su, C.-H. Lien, K.-H. Cheng, H.-T. Wu, T.-K. Ku, M.-J. Kao, and M.-J. Tsai, "A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability," in IEEE International Solid-State Circuits Conference (ISSCC), 2011.

[6]

R. Fackenthal, M. Kitagawa, W. Otsuka, W. K. Prall, D. Mills, K. Tsutsui, J. Javanifard, K. Tedrow, T. Tsushima, Y. Shibahara, G. Hush, "A 16Gb ReRAM with 200MB/s write and 1GB/s read in 27nm technology," in IEEE International Solid-State Circuits Conference (ISSCC), 2014.

[7]

T.-Y. Liu, T. H. Yan, R. Scheuerlein, Y. Chen, J. K. Lee, G. Balakrishnan, G. Yee, H. Zhang, A. Yap, J. Ouyang, T. Sasaki, S. Addepalli, A. Al-Shamma, C.-Y. Chen, M. Gupta, G. Hilton, S. Joshi, A. Kathuria, V. Lai, D. Masiwal, M. Matsumoto, et al., "A 130.7mm2 2-layer 32Gb ReRAM memory device in 24nm technology," in IEEE International Solid-State Circuits Conference (ISSCC), 2013.

[8]

A. Kawahara, R. Azuma, Y. Ikeda, K. Kawai, Y. Katoh, K. Tanabe, T. Nakamura, Y. Sumimoto, N. Yamada, N. Nakai, S. Sakamoto, Y. Hayakawa, K. Tsuji, S. Yoneda, A. Himeno, K. Origasa, K. Shimakawa, T. Takagi, T. Mikawa, and K. Aono, "An 8Mb multi-layered cross-point ReRAM macro with 443MB/s write throughput," in IEEE International Solid-State Circuits Conference (ISSCC), 2012.

[9]

A. Chen, "Comprehensive assessment of RRAM-based PUF for hardware security applications," in IEEE International Electron Devices Meeting (IEDM), 2015.

[10]

S. Yu, X. Guan, H.-S. P. Wong, "On the stochastic nature of resistive switching in metal oxide RRAM: physical modeling, Monte Carlo simulation, and experimental characterization," in IEEE International Electron Devices Meeting (IEDM), 2011.

[11]

C. Helfmeier, C. Boit, D. Nedospasov, J.-P. Seifert, "Cloning physically unclonable functions," in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2013.

[12]

W. Che, J. Plusquellic, S. Bhunia, "A Non-volatile memory based physically unclonable function without helper data," in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2014.

Digital Library

[13]

R. Liu, H. Wu, Y. Pang, H. Qian, S. Yu, "Experimental characterization of physical unclonable function based on 1kb resistive random access memory arrays," IEEE Electron Device Letters, vol. 36, no. 12, pp. 1380--1383, 2015.

[14]

A. Chen, "Utilizing the variability of resistive random access memory to implement reconfigurable physical unclonable functions," IEEE Electron Device Letters, vol. 36, no. 2, pp. 138--140, 2015.

[15]

A. Chen, "Reconfigurable physical unclonable function based on probabilistic switching of RRAM," IET Electronics Letters, vol. 51, no. 8, pp. 615--617, 2015.

[16]

R. Brederlow, R. Prakash, C. Paulus, R. Thewes, "A low-power true random number generator using random telegraph noise of single oxide-traps," in IEEE International Solid-State Circuits Conference (ISSCC), 2006.

[17]

J.-K. Lee, J.-W. Lee, J. Park, S.-W. Chung, J. S. Roh, S.-J. Hong, I.-w. Cho, H.-I Kwon, J.-H. Lee, "Extraction of trap location and energy from random telegraph noise in amorphous TiOx resistance random access memories," Applied Physics Letters, vol. 98, p. 143502, 2011.

[18]

S. Choi, Y. Yang, W. Lu, "Random telegraph noise and resistance switching analysis of oxide based resistive memory," Nanoscale, vol. 6, p. 400--404, 2013.

[19]

D. Veksler, G. Bersuker, L. Vandelli, A. Padovani, L. Larcher, A. Muraviev, B. Chakrabarti, E. Vogel, "Random telegraph noise (RTN) in scaled RRAM devices," in IEEE International Reliability Physics Symposium (IRPS), 2013.

[20]

N. Raghavan, R. Degraeve, A. Fantini, L. Goux, S. Strangio, B. Govoreanu, D.J. Wouters, G. Groeseneken, M. Jurczak, "Microscopic origin of random telegraph noise fluctuations in aggressively scaled RRAM and its impact on read disturb variability," in IEEE International Reliability Physics Symposium (IRPS), 2013.

[21]

S. Ambrogio, S. Balatti, A. Cubeta, A. Calderoni, N. Ramaswamy, D. Ielmini, "Statistical Fluctuations in HfOx Resistive-Switching Memory: Part II-Random Telegraph Noise," IEEE Transactions on Electron Devices, vol. 61, no. 8, pp. 2920--2927, 2014.

[22]

C.-Y. Huang, W. C. Shen, Y.-H. Tseng, Y.-C. King, C.-J. Lin, "A contact-resistive random-access-memory-based true random number generator," IEEE Electron Device Letters, vol. 33, no. 8, pp. 1108--1110, 2012.

Cited By

Ahsan SHossain THasan MHoque T(2023)Resistive RAM-based PUF: Challenges and Opportunities2023 IEEE 16th Dallas Circuits and Systems Conference (DCAS)10.1109/DCAS57389.2023.10130179(1-6)Online publication date: 14-Apr-2023
https://doi.org/10.1109/DCAS57389.2023.10130179
Yang FWang YWang CMa YWang XMiao X(2022)High-Entropy True Random Number Generator Based on Memristor Reset SwitchingIEEE Electron Device Letters10.1109/LED.2022.319534743:9(1459-1462)Online publication date: Sep-2022
https://doi.org/10.1109/LED.2022.3195347
John RShah NVishwanath SNg SFebriansyah BJagadeeswararao MChang CBasu AMathews N(2021)Halide perovskite memristors as flexible and reconfigurable physical unclonable functionsNature Communications10.1038/s41467-021-24057-012:1Online publication date: 17-Jun-2021
https://doi.org/10.1038/s41467-021-24057-0
Show More Cited By

Index Terms

Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Non-volatile memory
2. Security and privacy
  1. Security in hardware
    1. Hardware attacks and countermeasures

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cover image ACM Conferences

GLSVLSI '16: Proceedings of the 26th edition on Great Lakes Symposium on VLSI

May 2016

462 pages

ISBN:9781450342742

DOI:10.1145/2902961

General Chairs:
Ayse K. Coskun
Boston University, USA
,
Martin Margala
University of Massachusetts, Lowell, USA
,
Program Chairs:
Laleh Behjat
University of Calgary, Canada
,
Jie Han
University of Alberta, Canada

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 18 May 2016

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GLSVLSI '16: Great Lakes Symposium on VLSI 2016

May 18 - 20, 2016

Massachusetts, Boston, USA

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GLSVLSI '16 Paper Acceptance Rate 50 of 197 submissions, 25%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Ahsan SHossain THasan MHoque T(2023)Resistive RAM-based PUF: Challenges and Opportunities2023 IEEE 16th Dallas Circuits and Systems Conference (DCAS)10.1109/DCAS57389.2023.10130179(1-6)Online publication date: 14-Apr-2023
https://doi.org/10.1109/DCAS57389.2023.10130179
Yang FWang YWang CMa YWang XMiao X(2022)High-Entropy True Random Number Generator Based on Memristor Reset SwitchingIEEE Electron Device Letters10.1109/LED.2022.319534743:9(1459-1462)Online publication date: Sep-2022
https://doi.org/10.1109/LED.2022.3195347
John RShah NVishwanath SNg SFebriansyah BJagadeeswararao MChang CBasu AMathews N(2021)Halide perovskite memristors as flexible and reconfigurable physical unclonable functionsNature Communications10.1038/s41467-021-24057-012:1Online publication date: 17-Jun-2021
https://doi.org/10.1038/s41467-021-24057-0
Shen ZZhao CQi YXu WLiu YMitrovic IYang LZhao C(2020)Advances of RRAM Devices: Resistive Switching Mechanisms, Materials and Bionic Synaptic ApplicationNanomaterials10.3390/nano1008143710:8(1437)Online publication date: 23-Jul-2020
https://doi.org/10.3390/nano10081437
Gao YAl-Sarawi SAbbott D(2020)Physical unclonable functionsNature Electronics10.1038/s41928-020-0372-53:2(81-91)Online publication date: 24-Feb-2020
https://doi.org/10.1038/s41928-020-0372-5
Mahmoodi MStrukov DKavehei O(2019)Experimental Demonstrations of Security Primitives With Nonvolatile MemoriesIEEE Transactions on Electron Devices10.1109/TED.2019.294895066:12(5050-5059)Online publication date: Dec-2019
https://doi.org/10.1109/TED.2019.2948950
Kim JNili HTruong NAhmed TYang JJeong DSriram SRanasinghe DIppolito SChun HKavehei O(2019)Nano-Intrinsic True Random Number Generation: A Device to Data StudyIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2019.289504566:7(2615-2626)Online publication date: Jul-2019
https://doi.org/10.1109/TCSI.2019.2895045
Kaya ZTekin SKalem S(2018)Design of an FPGA-based RRAM parameter measurement platform2018 IEEE International Conference on Industrial Technology (ICIT)10.1109/ICIT.2018.8352386(1407-1411)Online publication date: Feb-2018
https://doi.org/10.1109/ICIT.2018.8352386
Chen YWang YZhang WChen Y(Helen) Li H(2017)In-place Logic Obfuscation for Emerging Nonvolatile FPGAsFundamentals of IP and SoC Security10.1007/978-3-319-50057-7_11(277-293)Online publication date: 25-Jan-2017
https://doi.org/10.1007/978-3-319-50057-7_11

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