Leakage Power Reduction Technique by using FinFET Technology
Article No.: 15, Pages 1 - 5
Abstract
Deep Sub Micron (DSM) technology demands for lower supply voltage, reduced threshold voltage and high transistor density which leads to exponentially increase in leakage power when circuit is in standby mode. To overcome from this situation Double Gate (DG) device like FinFET is used which have good control over the thin silicon fins with two tightly coupled gate, which mitigate shorter channel effect and exponentially reduces the leakage current. In this paper we utilize the property of FinFET in domino logic, for high speed operation and reduction of power consumption in large fan-in domino OR logic. We have proposed a circuit which is simulated in FinFET technology by BISM4 model using HSPICE at 32nm process technology at 250C with CL=1pF at 100MHz frequency. For 8 and 16 input OR gate we save average power 11.5%,11.39% SFLD, 22.97%, 18.12% HSD, 30.90%,34.57% CKD in SP mode. For LP mode 11.26%, 15.78% SFLD, 19.74%, 17.94% HSD, 45.23%, 34.69% CKD respectively.
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- Leakage Power Reduction Technique by using FinFET Technology
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Published In
March 2016
843 pages
ISBN:9781450339629
DOI:10.1145/2905055
Copyright © 2016 ACM.
© 2016 Association for Computing Machinery. ACM acknowledges that this contribution was authored or co-authored by an employee, contractor or affiliate of a national government. As such, the Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only.
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Association for Computing Machinery
New York, NY, United States
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Published: 04 March 2016
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- MANIT Bhoapl
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ICTCS '16
ICTCS '16: Second International Conference on Information and Communication Technology for Competitive Strategies
March 4 - 5, 2016
Udaipur, India
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