Design of Low Power Memristor Non-Volatile Dram Cell with Footer Switch
Article No.: 90, Pages 1 - 6
Abstract
In this paper Memristor based non-volatile DRAM was proposed. DRAM has low transistor count per cell compared to SRAM which promotes Moore's law in VLSI designs. The main drawback is its dynamic nature, hence the need for signal refreshing. The reduction of charge on the storage capacitor is due to leakage. The fast feature size scaling has caused sharp increase in the leakage, resulting in need for the leakage power to be treated carefully. In this research besides adding the non-volatile property to the 3T1D DRAM cell, a method to reduce idle power using sleeper transistor was also propose hence the designing of the 5T1D1M cell. The circuit achieves this by reducing the idle leakage current with the use of FinFETs and sleepy keeper transistor. The designs and simulations were done with the help of cadence virtuoso tool at 45nm technology.
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- Design of Low Power Memristor Non-Volatile Dram Cell with Footer Switch
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Published In
March 2016
843 pages
ISBN:9781450339629
DOI:10.1145/2905055
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Published: 04 March 2016
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ICTCS '16
ICTCS '16: Second International Conference on Information and Communication Technology for Competitive Strategies
March 4 - 5, 2016
Udaipur, India
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