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Design of Low Power Memristor Non-Volatile Dram Cell with Footer Switch

Published: 04 March 2016 Publication History

Abstract

In this paper Memristor based non-volatile DRAM was proposed. DRAM has low transistor count per cell compared to SRAM which promotes Moore's law in VLSI designs. The main drawback is its dynamic nature, hence the need for signal refreshing. The reduction of charge on the storage capacitor is due to leakage. The fast feature size scaling has caused sharp increase in the leakage, resulting in need for the leakage power to be treated carefully. In this research besides adding the non-volatile property to the 3T1D DRAM cell, a method to reduce idle power using sleeper transistor was also propose hence the designing of the 5T1D1M cell. The circuit achieves this by reducing the idle leakage current with the use of FinFETs and sleepy keeper transistor. The designs and simulations were done with the help of cadence virtuoso tool at 45nm technology.

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  1. Design of Low Power Memristor Non-Volatile Dram Cell with Footer Switch

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    ICTCS '16: Proceedings of the Second International Conference on Information and Communication Technology for Competitive Strategies
    March 2016
    843 pages
    ISBN:9781450339629
    DOI:10.1145/2905055
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 04 March 2016

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    Author Tags

    1. 4T1D1M
    2. 5T1D1M
    3. DRAM
    4. leakage current
    5. memristor
    6. non-volatile memory
    7. sleepy transistor

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