Modeling and implementation of a fully-digital integrated per-core voltage regulation system in a 28nm high performance 64-bit processor
Authors: 
Ravinder Rachala, Miguel Rodriguez, Stephen Kosonocky, Milos TrajkovicAuthors Info & Claims
Ravinder Rachala, Miguel Rodriguez, Stephen Kosonocky, Milos TrajkovicAuthors Info & ClaimsPages 88 - 93
Abstract
This paper describes modeling and implementation of a fully digital integrated linear voltage regulation system implemented in a 28nm x86-64 core to reduce power gating entry or exit latency. Running on a 100 MHz clock, the controller samples voltage using a time-to-digital converter, and controls a set of PFETs organized in a ring topology around the CPU cores to drop voltage down to a specified target value. A simple analytical model is developed and validated through fast Matlab-Simulink simulation, enabling quick design turnaround and reducing schedule impact.
The regulation system is designed to support input-output voltages in the range 1.3 V - 0.55 V. Digitally-controlled header resistance values range from 1.5 Ω to 2 mΩ. Stable processor behavior is observed down to 0.6 V, enabling fast pseudo-power gating entry and exit. In a high-performance x86-64 dual-core microprocessor chip, the controller enables an effective 6% frequency increase for lightly threaded applications by increasing the boost state residency.
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Index Terms
- Modeling and implementation of a fully-digital integrated per-core voltage regulation system in a 28nm high performance 64-bit processor
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Published In
August 2016
392 pages
ISBN:9781450341851
DOI:10.1145/2934583
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Published: 08 August 2016
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ISLPED '16
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ISLPED '16: International Symposium on Low Power Electronics and Design
August 8 - 10, 2016
CA, San Francisco Airport, USA
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ISLPED '16 Paper Acceptance Rate 60 of 190 submissions, 32%;
Overall Acceptance Rate 398 of 1,159 submissions, 34%
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