ABSTRACT
We present a non-volatile flip-flop with a feature to back-up the state in a ferroelectric transistor (FEFET) during power failure or supply gating. The data is stored in the form of polarization of the ferroelectric (FE) layer in the gate stack of the FEFET. The proposed flip-flop utilizes the non-volatility of the three-terminal FEFET to optimize the data backup and restore operations. We perform an extensive device-circuit analysis to provide insights into the design of the proposed flip-flop. We discuss the optimization of the FE thickness in the gate stack of the FEFET to introduce suitable non-volatility and present the implications at the circuit level. Our analysis shows that by virtue of the three terminal structure of the FEFET and the order of magnitude difference in the current for the two polarization states, the design of the backup/restore module is considerably simplified. Compared to a FE capacitor based non-volatile flip-flop, the proposed flip-flop achieves 40%--50% smaller backup delay, 27%--40% lower backup energy, comparable restore delay and up to an order of magnitude lower restore energy. While the FE capacitor based design leads to 76% area penalty compared to a conventional (volatile) flip-flop, the proposed design incurs only 35% area overhead.
- T. Jhaveri, et al, "Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings," IEEE Trans. Computer-Aided Des Int. Circ. and Sys,vol. 29, no. 4, pp. 509--527, 2010. Google ScholarDigital Library
- B. Rajamohanan et al., "0.5 V Supply Voltage Operation of In0.65Ga0.35As/GaAs0.4Sb0.6 Tunnel FET," IEEE Electron Device Letters, vol. 36, no. 1, pp. 20--22, Jan. 2015.Google ScholarCross Ref
- A. B. Andrew et al, "Growth and transport properties of complementary germanium nanowire field-effect transistors", Appl. Phys. Lett., 84, 4176 (2004).Google ScholarCross Ref
- S. Salahuddin and S. Datta, "Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices", Nano Lett., 2008, 8 (2), pp 405--410.Google ScholarCross Ref
- A. Khan, et al, "Experimental evidence of ferroelectricnegative capacitance in nanoscale heterostructures", Appl.Phys. Lett. 99, 113501 (2011).Google ScholarCross Ref
- S. L. Miller and P. J. McWhorter, "Physics of the ferroelectric nonvolatile memory field effect transistor", J. Appl. Phys., 72, 5999 (1992).Google ScholarCross Ref
- S. Henzler et al., "Dynamic state-retention flip-flop for finegrained power gating with small design and power overhead," IEEE Journal of Solid-State Circuits, vol. 41, no. 7, pp. 1654--1661, July 2006.Google ScholarCross Ref
- Y. Liu et al, "Ambient energy harvesting nonvolatile processors: from circuit to system", Design Automation Conference, 2015. Google ScholarDigital Library
- K. Ma et al., "Architecture exploration for ambient energy harvesting nonvolatile processors," High Performance Computer Architecture, 2015, pp. 526--537.Google Scholar
- K.-W Kwon et al, "SHE-NVFF: Spin Hall Effect-Based Nonvolatile Flip-Flop for Power Gating Architecture", IEEE Electron Device Letters, vol. 35, no. 4, 2014. pp: 488--490.Google ScholarCross Ref
- Y. Wang et al., "A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops," ESSCIRC, 2012, pp. 149--152.Google Scholar
- H. Kimura et al, "Highly Reliable Non-Volatile Logic Circuit Technology and Its Application", Int. Symp.Mult.-Valued Logic, 2013, pp: 212--218. Google ScholarDigital Library
- A. I. Khan, et al, "Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation," Int. Electron Devices Meeting, 2011, pp. 11.3.1--11.3.4Google Scholar
- T. K. Song, "Landau-Khalatnikov Simulations for Ferroelectric Switching in Ferroelectric Random Access Memory Application", Journal of the Korean Physical Society, vol. 46, no. 1, pp. 5~9, 2005.Google Scholar
- https://www.mosis.com/files/scmos/scmos.pdfGoogle Scholar
- J. Li, et al "Ultrafast polarization switching in thin-film ferroelectrics", App. Phys Lett, vol. 84, no. 7, pp: 1174--1176, Feb 2004.Google ScholarCross Ref
- A. Aziz, et al, "Physics-Based Circuit-Compatible SPICE Model for Ferroelectric Transistors," IEEE Electron Device Letters, vol. 37, no. 6, pp. 805--808, June 2016.Google Scholar
- http://ptm.asu.eduGoogle Scholar
Index Terms
- Ferroelectric Transistor based Non-Volatile Flip-Flop
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