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Performance Impact of Magnetic and Thermal Attack on STTRAM and Low-Overhead Mitigation Techniques

Published: 08 August 2016 Publication History

Abstract

In this paper, we analyze the fundamental vulnerabilities of Spin-Torque-Transfer RAM on magnetic field and temperature that can be exploited by adversaries with an intent to trigger soft performance failures. We present novel attack vectors and their impact on memory performance (i.e., read, write and retention). We propose a novel low-overhead clock frequency-adaptation technique to mitigate the attack. Our analysis indicate slowing the clock frequency by 85% restores 170 mV of sense margin under 300 Oe DC magnetic field. In addition, 66% operating clock slowdown allows STTRAM to tolerate over 300 Oe AC magnetic field.

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Cited By

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  • (2024)Assessing Magnetic Attack on Commercial 40nm pMTJ STT-MRAM2024 IEEE Physical Assurance and Inspection of Electronics (PAINE)10.1109/PAINE62042.2024.10792779(1-6)Online publication date: 12-Nov-2024
  • (2021)Towards Enhanced System Efficiency while Mitigating Row HammerACM Transactions on Architecture and Code Optimization10.1145/345874918:4(1-26)Online publication date: 17-Jul-2021
  • (2020)Security of Emerging Memory ChipsEmerging Topics in Hardware Security10.1007/978-3-030-64448-2_14(357-390)Online publication date: 10-Nov-2020
  • Show More Cited By

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  1. Performance Impact of Magnetic and Thermal Attack on STTRAM and Low-Overhead Mitigation Techniques

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          cover image ACM Conferences
          ISLPED '16: Proceedings of the 2016 International Symposium on Low Power Electronics and Design
          August 2016
          392 pages
          ISBN:9781450341851
          DOI:10.1145/2934583
          Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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          Published: 08 August 2016

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          ISLPED '16: International Symposium on Low Power Electronics and Design
          August 8 - 10, 2016
          CA, San Francisco Airport, USA

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          ISLPED '16 Paper Acceptance Rate 60 of 190 submissions, 32%;
          Overall Acceptance Rate 398 of 1,159 submissions, 34%

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          View all
          • (2024)Assessing Magnetic Attack on Commercial 40nm pMTJ STT-MRAM2024 IEEE Physical Assurance and Inspection of Electronics (PAINE)10.1109/PAINE62042.2024.10792779(1-6)Online publication date: 12-Nov-2024
          • (2021)Towards Enhanced System Efficiency while Mitigating Row HammerACM Transactions on Architecture and Code Optimization10.1145/345874918:4(1-26)Online publication date: 17-Jul-2021
          • (2020)Security of Emerging Memory ChipsEmerging Topics in Hardware Security10.1007/978-3-030-64448-2_14(357-390)Online publication date: 10-Nov-2020
          • (2018)Analysis of Row Hammer Attack on STTRAM2018 IEEE 36th International Conference on Computer Design (ICCD)10.1109/ICCD.2018.00021(75-82)Online publication date: Oct-2018
          • (2017)Investigation of magnetic field attacks on commercial Magneto-Resistive Random Access Memory2017 18th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2017.7918309(155-160)Online publication date: Mar-2017
          • (2017)Side-Channel Attack on STTRAM Based Cache for Cryptographic Application2017 IEEE International Conference on Computer Design (ICCD)10.1109/ICCD.2017.14(33-40)Online publication date: Nov-2017
          • (2017)Replacing eFlash with STTRAM in IoTs: Security Challenges and SolutionsJournal of Hardware and Systems Security10.1007/s41635-017-0026-x1:4(328-339)Online publication date: 20-Nov-2017
          • (2016)Spintronics and Security: Prospects, Vulnerabilities, Attack Models, and PreventionsProceedings of the IEEE10.1109/JPROC.2016.2583419104:10(1864-1893)Online publication date: Oct-2016

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