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A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip Interconnects
Photonic devices fabricated with back-end compatible silicon photonic (BCSP) materials can provide independence from the complex CMOS front-end compatible silicon photonic (FCSP) process, to significantly enhance photonic network-on-chip (PNoC) ...
Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient Circuits
Dynamic voltage scaling (DVS) has become one of the most effective approaches to achieve ultra-low-power SoC. To eliminate timing errors arising from DVS, several error-resilient circuit design techniques were proposed to detect and/or correct timing ...
Connectivity Effects on Energy and Area for Neuromorphic System with High Speed Asynchronous Pulse Mode Links
Hardware neuromorphic systems are challenged to achieve biologically realistic levels of interconnectivity. When building a physical implementation of a neural net, the properties of the media immediately impose limits on the number of interconnects and ...
Buffered Interconnects in 3D IC Layout Design
A very important challenge in designing through-silicon via (TSV)-based 3D ICs is to accurately estimate, through all stages of the physical design, the interconnect delay which is strongly dependent on the layout of 3D IC. The earlier in the design ...
Topologically-Geometric Routing
The paper introduces foundations of the "Flexible Routing Method" that belongs to the topologically-geometric type. It develops the idea to divide the routing problem on two separate successive stages: topological and geometrical. At the first stage it ...
Revisiting 3DIC Benefit with Multiple Tiers
3DICs with multiple tiers are expected to achieve large benefits (e.g., in terms of power, area) as compared to conventional planar designs. However, few if any previous works study upper bounds on power and area benefits from 3DIC integration with ...
Spin-Hall Assisted STT-RAM Design and Discussion
In recent years, Spin-Transfer Torque Random Access Memory (STT-RAM) has attracted significant attentions from both industry and academia due to its attractive attributes such as small cell area and non-volatility. However, long switching time and large ...
A Demand-Aware Predictive Dynamic Bandwidth Allocation Mechanism for Wireless Network-on-Chip
Long distance data communication over multi-hop wireline paths in conventional Networks-on-Chips (NoCs) cause high energy consumption and degradation in bandwidth. Wireless interconnects in the millimeter-wave band have emerged as an energy-efficient ...
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Acceptance Rates
Year | Submitted | Accepted | Rate |
---|---|---|---|
SLIP '18 | 8 | 6 | 75% |
Overall | 8 | 6 | 75% |