research-article

Allocation of multi-bit flip-flops in logic synthesis for power optimization

Authors:

Dongyoun Yi,

Taewhan KimAuthors Info & Claims

2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Pages 1 - 6

https://doi.org/10.1145/2966986.2966998

Published: 07 November 2016 Publication History

Abstract

In this paper, a new approach to the problem of allocating multi-bit flip-flops for data storage is presented. Previous approaches divide the allocation problem into two separate steps: (i) placing single-bit flip-flops under circuit timing constraints and (ii) minimizing the flip-flop and clock tree power by grouping single-bit flip-flops to form multi-bit flip-flops. Yet, there is no easy way to predict the result of step (ii) during step (i). In our approach, we place primary importance on the cost of power consumption. Consequently, we try to minimize power consumption by synthesizing multi-bit flip-flops first and then to place them later. For a number of benchmark circuits, it is shown that our approach of early consideration of synthesizing multi-bit flip-flops is very effective, reducing the clock power by 13.5% while satisfying all the timing constraints.

6. References

[1]

Y.-T. Chang, C.-C. Hsu, M. P.-H. Lin, Y.-W. Tsai, and S.-F. Chen. Post-placement power optimization with multi-bit flip-flops. In IEEE/ACM ICCAD, 2010.

Google Scholar

[2]

Z.-W. Chen and J.-T. Yan. Routability-constrained multi-bit flip-flop construction for clock power reduction. Integration, the VLSI Journal, 46 (3), 2013.

Google Scholar

[3]

M. R. Garey and D. S. Johnson. Computers and intractability: a guide to the theory of np-completeness. San Francisco, LA: Freeman, 1979.

Google Scholar

[4]

C.-C. Hsu, Y.-C. Chen, and M. P.-H. Lin. In-placement clock-tree aware multi-bit flip-flop generation for power optimization. In IEEE/ACM ICCAD, 2013.

Google Scholar

[5]

Y. Kretchmer and L. Logic. Using multi-bit register inference to save area and power: the good, the bad, and the ugly. EE Times Asia, 2001.

Google Scholar

[6]

M. P.-H. Lin, C.-C. Hsu, and Y.-T. Chang. Recent research in clock power saving with multi-bit flip-flops. In IEEE MWSCAS, 2011.

Google Scholar

[7]

M. P.-H. Lin, C.-C. Hsu, and Y.-C. Chen. Clock-tree aware multibit flip-flop generation during placement for power optimization. IEEE TCAD, 34 (2), 2015.

Google Scholar

[8]

H. Moon and T. Kim. Design and allocation of loosely coupled multi-bit flip-flops for power reduction in post-placement optimizationi. In IEEE ASPDAC, 2016.

Google Scholar

[9]

Y.-T. Shyu, J.-M. Lin, C.-P. Huang, C.-W. Lin, Y.-Z. Lin, and S.-J. Chang. Effective and efficient approach for power reduction by using multi-bit flip-flops. IEEE TVLSI, 21 (4), 2013.

Google Scholar

Cited By

View all

Kim SKim T(2025)Design and Utilization of Multiskewed Multibit Flip-Flop Cells for Timing Optimization: Design and Technology Co-Optimization ApproachIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.345783444:3(1084-1097)Online publication date: Mar-2025
https://doi.org/10.1109/TCAD.2024.3457834
Kim SKim T(2024)Enhancing Design Qualities Utilizing Multibit Flip-Flops: A Design and Technology Co-Optimization Driven ApproachIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.333853243:5(1538-1551)Online publication date: May-2024
https://doi.org/10.1109/TCAD.2023.3338532
Hyun DKoh SJung YKim TShin Y(2023)Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop StackingACM Transactions on Design Automation of Electronic Systems10.1145/357338728:4(1-19)Online publication date: 17-May-2023
https://dl.acm.org/doi/10.1145/3573387
Show More Cited By

Index Terms

Allocation of multi-bit flip-flops in logic synthesis for power optimization
1. Applied computing
  1. Physical sciences and engineering
    1. Engineering
2. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
    2. Logic synthesis
      1. Circuit optimization
  2. Integrated circuits
    1. Logic circuits

Index terms have been assigned to the content through auto-classification.

Recommendations

Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization
ICCAD '22: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design

Multi-bit flip-flops (MBFFs) are often used to reduce the number of clock sinks, resulting in a low-power design. A traditional MBFF is composed of individual FFs of uniform driving strength. However, if some but not all of the bits of an MBFF violate ...
Flip-Flops for Multiple-Valued Logic

A family of multiple-valued (MV) electronic memory elements, referred to herein as flip-flops, is presented along with a system of MV algebra upon which they are based. These MV flip-flops are compared to binary flip-flops. MV asynchronous set-clear ...
Design and allocation of loosely coupled multi-bit flip-flops for power reduction in post-placement optimization
2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)
Merging 1-bit flip-flops into multi-bit flip-flops in the post-placement stage is one of the most effective techniques for minimizing clock power. The obstacles that hinder the merging process for multi-bit flip-flops are (1) the input and output timing ...

Comments

Information & Contributors

Information

Published In

2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Nov 2016

946 pages

Publisher

IEEE Press

Publication History

Published: 07 November 2016

Permissions

Request permissions for this article.

Request Permissions

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

9
Total Citations
View Citations
130
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 27 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Kim SKim T(2025)Design and Utilization of Multiskewed Multibit Flip-Flop Cells for Timing Optimization: Design and Technology Co-Optimization ApproachIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.345783444:3(1084-1097)Online publication date: Mar-2025
https://doi.org/10.1109/TCAD.2024.3457834
Kim SKim T(2024)Enhancing Design Qualities Utilizing Multibit Flip-Flops: A Design and Technology Co-Optimization Driven ApproachIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.333853243:5(1538-1551)Online publication date: May-2024
https://doi.org/10.1109/TCAD.2023.3338532
Hyun DKoh SJung YKim TShin Y(2023)Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop StackingACM Transactions on Design Automation of Electronic Systems10.1145/357338728:4(1-19)Online publication date: 17-May-2023
https://dl.acm.org/doi/10.1145/3573387
Kim JKim T(2023)Allocation of Multi-bit Flip-Flops Targeting Low-Power Chips2023 20th International SoC Design Conference (ISOCC)10.1109/ISOCC59558.2023.10395980(121-122)Online publication date: 25-Oct-2023
https://doi.org/10.1109/ISOCC59558.2023.10395980
Liu MLai YMak WWang TMitra TYoung EXiong J(2022)Generation of Mixed-Driving Multi-Bit Flip-Flops for Power OptimizationProceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design10.1145/3508352.3549473(1-9)Online publication date: 30-Oct-2022
https://dl.acm.org/doi/10.1145/3508352.3549473
Kim SKim T(2022)Optimizing Timing in Placement Through I/O Signal Flipping on Multi-bit Flip-flops2022 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS48785.2022.9937267(2623-2624)Online publication date: 28-May-2022
https://doi.org/10.1109/ISCAS48785.2022.9937267
Seitanidis IDimitrakopoulos GMattheakis PMasse-Navette LChinnery D(2019)Timing-Driven and Placement-Aware Multibit Register CompositionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.285274038:8(1501-1514)Online publication date: Aug-2019
https://doi.org/10.1109/TCAD.2018.2852740
Guo RArcher BChau KCai X(2018)Efficient Cell-Aware Defect Characterization for Multi-bit Cells2018 IEEE International Test Conference in Asia (ITC-Asia)10.1109/ITC-Asia.2018.00012(7-12)Online publication date: Aug-2018
https://doi.org/10.1109/ITC-Asia.2018.00012
Seitanidis IDimitrakopoulos GMattheakis PMasse-Navete LChinnery D(2017)Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulationProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062327(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3062327

Abstract

6. References

Cited By

Index Terms

Recommendations

Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization

Flip-Flops for Multiple-Valued Logic

Design and allocation of loosely coupled multi-bit flip-flops for power reduction in post-placement optimization

Comments

Information

Published In

Publisher

Publication History

Permissions

Qualifiers

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

Share

Share this Publication link

Share on social media

Affiliations