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Are proximity attacks a threat to the security of split manufacturing of integrated circuits?

Published: 07 November 2016 Publication History

Abstract

Split manufacturing is a technique that allows manufacturing the transistor-level and lower metal layers of an IC at a high-end, untrusted foundry, while manufacturing only the higher metal layers at a smaller, trusted foundry. Using split manufacturing is only viable if the untrusted foundry cannot reverse engineer the higher metal layer connections (and thus the overall IC design) from the lower layers. This work studies the effectiveness of proximity attack as a key step to reverse engineer a design at the untrusted foundry. We propose and study different proximity attacks based on how a set of candidates are defined for each broken connection. The attacks use both placement and routing information along with factors which capture the router's behavior such as per-layer routing congestion. Our studies are based on designs having millions of nets routed across 9 metal layers and significant layer-by-layer wire size variation. Our results show that a common, Hamming Distance-based proximity attack seldom achieves a match rate over 5%. But our proposed attack yields a relatively-small list of candidates which often contains the correct match. Finally, we propose a procedure to artificially insert routing blockages in a design at a desired split level, without causing any area overhead, in order to trick the router to make proximity-based reverse engineering significantly more challenging.

7. References

[1]
C. J. Alpert and G. E. Tellez. The importance of routing congestion analysis. In DAC. COM Knowledge Center Article, 2010.
[2]
C. Clavier, Q. Isorez, D. Marion, and A. Wurcker. Complete reverse-engineering of AES-like block ciphers by SCARE and FIRE attacks. Cryptography and Communications, 7 (1): 121–162, 2015.
[3]
K.-R. Dai, W.-H. Liu, and Y.-L. Li. NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing. IEEE Trans. on VLSI, 20 (3): 459–472, 2012.
[4]
F. Imeson, A. Emtenan, S. Garg, and M. V. Tripunitara. Securing computer hardware using 3D integrated circuit (IC) technology and split manufacturing for obfuscation. In USE NIX Conf. on Security, pages 495–510, 2013.
[5]
M. Jagasivamani, P. Gadfort, M. Sika, M. Bajura, and M. Fritze. Split-fabrication obfuscation: Metrics and techniques. In International Symp. on Hardware-Oriented Security and Trust, pages 7–12, 2014.
[6]
W.-H. Liu, W.-C. Kao, Y.-L. Li, and K.-Y. Chao. NCTU-GR 2.0: Multithreaded collision-aware global routing with bounded-length maze routing. IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (5): 709–722, 2013.
[7]
J. Rajendran, O. Sinanoglu, and R. Karri. Is split manufacturing secure? In Design, Automation and Test in Europe, pages 1259–1264, 2013.
[8]
M. Tehranipoor and F. Koushanfar. A survey of hardware Trojan taxonomy and detection. IEEE Design 8 Test of Computers, 27 (1): 10–25, 2010.
[9]
R. Torrance and D. James. The state-of-the-art in semiconductor reverse engineering. In Design Automation Conf., pages 333–338, 2011.
[10]
K. Vaidyanathan, R. Liu, E. Sumbul, Q. Zhu, F. Franchetti, and L. Pileggi. Efficient and secure intellectual property (IP) design with split fabrication. In International Symp. on Hardware-Oriented Security and Trust. pages 13–18, 2014.
[11]
N. Viswanathan, C. J. Alpert, C. C. N. Sze, Z. Li, G.-J. Nam, and J. A. Roy. The ISPD-2011 routability-driven placement contest and benchmark suite. In International Symp. on Physical Design, pages 141–146, 2011.
[12]
Y. Wang, P. Chen, J. Hu, and J. Rajendran. The cat and mouse in split manufacturing. In Design Automation Conf., page 165, 2016.
[13]
X. Zhang and M. Tehranipoor. Case study: Detecting hardware Trojans in third-party digital IP cores. In International Symp. on Hardware-Oriented Security and Trust, pages 67–70, 2011.

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          cover image Guide Proceedings
          2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
          Nov 2016
          946 pages

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          IEEE Press

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          Published: 07 November 2016

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          • (2023)UN-SPLIT: Attacking Split Manufacturing Using Link Prediction in Graph Neural NetworksSecurity, Privacy, and Applied Cryptography Engineering10.1007/978-3-031-51583-5_12(197-213)Online publication date: 14-Dec-2023
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