research-article

BoostNoC: Power efficient network-on-chip architecture for near threshold computing

Authors:

Chidhambaranathan Rajamanikkam,

Koushik Chakraborty,

Sanghamitra RoyAuthors Info & Claims

2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Pages 1 - 8

https://doi.org/10.1145/2966986.2967009

Published: 07 November 2016 Publication History

Abstract

While near threshold design space provides a promising approach towards energy-efficient computing, it is plagued by sub-optimal performance. Application characteristics and hardware non-idealities of conventional architectures (optimized for the nominal voltage) prevent us from fully leveraging the potential of NTC systems. Further, the popular approach of increasing the computational core count to compensate for the performance loss severely burdens the on-chip communication fabric with an increased communication demand. In this work, we quantitatively analyze the performance bottleneck created by a conventional NoC architecture in many-core NTC systems. To reclaim the performance lost due to a sub-optimal NoC, we propose BoostNoC — a power efficient, multi-layered network-on-chip architecture. BoostNoC improves the system performance by nearly 2× over a conventional NTC system. Further, we improve the energy efficiency by 1.4× with the use of drowsy routers.

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Cited By

Bhamidipati PKaranth A(2022)HREN: A Hybrid Reliable and Energy-Efficient Network-on-Chip ArchitectureIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2022.3147407(1-1)Online publication date: 2022
https://doi.org/10.1109/TETC.2022.3147407
Lin NLu HWei XLi XShibuya T(2019)Redeeming chip-level power efficiency by collaborative management of the computation and communicationProceedings of the 24th Asia and South Pacific Design Automation Conference10.1145/3287624.3287647(376-381)Online publication date: 21-Jan-2019
https://dl.acm.org/doi/10.1145/3287624.3287647
Lu HChang YYan GLin NWei XLi X(2019)ShuttleNoC: Power-Adaptable Communication Infrastructure for Many-Core ProcessorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.285516538:8(1438-1451)Online publication date: Aug-2019
https://doi.org/10.1109/TCAD.2018.2855165
Show More Cited By

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cover image Guide Proceedings

2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Nov 2016

946 pages

Copyright © 2016.

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IEEE Press

Publication History

Published: 07 November 2016

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Cited By

Bhamidipati PKaranth A(2022)HREN: A Hybrid Reliable and Energy-Efficient Network-on-Chip ArchitectureIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2022.3147407(1-1)Online publication date: 2022
https://doi.org/10.1109/TETC.2022.3147407
Lin NLu HWei XLi XShibuya T(2019)Redeeming chip-level power efficiency by collaborative management of the computation and communicationProceedings of the 24th Asia and South Pacific Design Automation Conference10.1145/3287624.3287647(376-381)Online publication date: 21-Jan-2019
https://dl.acm.org/doi/10.1145/3287624.3287647
Lu HChang YYan GLin NWei XLi X(2019)ShuttleNoC: Power-Adaptable Communication Infrastructure for Many-Core ProcessorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.285516538:8(1438-1451)Online publication date: Aug-2019
https://doi.org/10.1109/TCAD.2018.2855165
Rao NRamachandran AShah A(2018)MLNoC: A Machine Learning Based Approach to NoC Design2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)10.1109/CAHPC.2018.8645914(1-8)Online publication date: Sep-2018
https://doi.org/10.1109/CAHPC.2018.8645914

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