skip to main content
10.1145/2966986.2967037guideproceedingsArticle/Chapter ViewAbstractPublication PagesConference Proceedingsacm-pubtype
research-article

Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuits

Published: 07 November 2016 Publication History

Abstract

Numerous research efforts are targeting new devices that could continue performance scaling trends associated with Moore's Law and/or accomplish computational tasks with less energy. One such device is the ferroelectric FET (FeFET), which offers the potential to be scaled beyond the end of the silicon roadmap as predicted by ITRS. Furthermore, the I<inf>ds</inf> vs. V<inf>gs</inf> characteristics of FeFETs may allow a device to function as both a switch and a non-volatile storage element. We exploit this FeFET property to enable fine-grained logic-in-memory (LiM). We consider three different circuit design styles for FeFET-based LiM: complementary (differential), dynamic current mode, and dynamic logic. Our designs are compared with existing approaches for LiM (i.e., based on magnetic tunnel junctions (MTJs), CMOS, etc.) that afford the same circuit-level functionality. Assuming similar feature sizes, non-volatile FeFET-based LiM circuits are more efficient than functional equivalents based on MTJs when considering metrics such as propagation delay (2.9&#x00D7;, 6.8&#x00D7;) and dyanmic power (3.7&#x00D7;, 2.3&#x00D7;) (for 45 nm, 22 nm technology respectively). Compared to CMOS functional equivalents, FeFET designs still exhibit modest improvements in the aforementioned metrics while also offering non-volatility and reduced device count.

8. References

[1]
Logic-in-rram: Design of low-power circuits based on oxide memories. http://lsi.epfi.ch/page-79126-en.html. Accessed: 2016–04-20.
[2]
Systems on nanoscale information fabrics (SONIC). https://www.sonic-center.org/research/nano.php. Accessed: 2016–04-20.
[3]
M. Allam et al. Dynamic current mode logic (DyCML): a new low-power high-performance logic style. IEEE JSSC, 36 (3), March 2001.
[4]
M. M. S. Aly et al., Energy-efficient abundant-data computing: The n3xt 1,000x. Computer, 48 (12):24–33, Dec 2015.
[5]
R. Balasubramonian et al. Near-data processing: Insights from a micro-46 workshop. IEEE Micro, 34 (4):36–42, July 2014.
[6]
S. Borkar et al. The future of microprocessors. Commun. ACM, 54 (5):67–77, May 2011.
[7]
S. Crolles, France. Design Rule Manual for CMOS 40nm, 2012.
[8]
E. Deng et al., High-frequency low-power magnetic full-adder based on magnetic tunnel junction with spin-hall assistance. Magnetics, IEEE Transactions on, 51 (11):1–4, 2015.
[9]
E. Deng et al., Low power magnetic full-adder based on Spin Transfer Torque MRAM. IEEE Transaction on Magnetics, 49 (9), September 2013.
[10]
J. Draper et al., The architecture of the diva processing-in-memory chip. In Proceedings of the 16th International Conference on Supercomputing, ICS ‘02, pages 14–25, New York, NY, USA, 2002. ACM.
[11]
H. Esmaeilzadeh et al., Dark silicon and the end of multicore scaling. In ISCA, 2011 38th Annual International Symposium on, pages 365–376, June 2011.
[12]
M. Imani et al., Approximate computing using multiple-access single-charge associative memory. 2016.
[13]
M. Imani et al., Resistive configurable associative memory for approximate computing. In 2016 DATE, pages 1327–1332. IEEE, 2016.
[14]
A. I. Khan. Negative Capacitance for Ultra-low Power Computing. PhD thesis, University of California at Berkeley, 2015.
[15]
H. Kimura et al., Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI. IEEE JSSC, 39 (6), June 2004.
[16]
C. E. Kozyrakis et al., Scalable processors in the billion-transistor era: Iram. Computer, 30 (9):75–78, Sep 1997.
[17]
K. Ma et al., Architecture exploration for ambient energy harvesting nonvolatile processors. In 2015 HPCA, pages 526–537, Feb 2015.
[18]
S. Matsunaga et al., Fabrication of a non-volatile full adder based on logic-in-memory architecture using magnetic tunnel junctions. Applied Physics Express, 1.9 (9): 091301, August 2008.
[19]
S. Matsunaga et al., MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues. In DATE, pages 978-3–9810801-5-5, 2009.
[20]
S. Matsunaga et al., Design of a nine-transistor/two-magnetic-tunnel-junction-cell-based low-energy nonvolatile ternary content-addressable memory. Japanese J. of Applied Physics, 51 (2S):02BM06, 2012.
[21]
S. Matsunaga et al., A 3.14 um 2 4t-2mtj-cell fully parallel tcam based on nonvolatile logic-in-memory architecture. In VLSIC, 2012 Symposium on, pages 44–45. IEEE, 2012.
[22]
A. Mochizuki et al., Tmr-based logic-in-memory circuit for low-power vlsi. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., E88-A (6):1408–1415, 2005.
[23]
A. Mochizuki et al., TMR-based logic-in-memory circuit for low-power VLSI. ITC-CSCC, E88-A (6):1408–1415, June 2005.
[24]
J. T. Pawlowski. Hybrid memory cube (hmc). In Proceedinas of HotChips 23, 2011.
[25]
S. H. Pugsley et al., Ndc: Analyzing the impact of 3d-stacked memory+Iogic devices on mapreduce workloads. In 2014 ISPASS, pages 190–200, March 2014.
[26]
F. Ren et al. True energy-performance analysis of the MTJ-based logic-in-memory architecture (1-bit full adder). IEEE TED, 57 (5), May 2010.
[27]
S. Salahuddin et al. Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Letters, 8 (2):405–410, 2008.
[28]
T. Song. Landau-khalatnikov simulations for ferroelectric switching in ferroelectric random access memory application. Journal of the Korean Physical Society, 46 (1):5–9, 2005.
[29]
T. N. Theis et al. In quest of the next switch: Prospects for greatly reduced power dissipation in a successor to the silicon field-effect transistor. Proceedings of the IEEE, 98 (12):2005–2014, Dec 2010.
[30]
R. Vattikonda et al., Modeling and minimization of PMOS NBTI effect for robust nanometer design [Online] http:/yptrn.asu.edu/. In DAC, pages 1047–1052, 2006.
[31]
Z. Wang et al., A physics-based compact model of ferroelectric tunnel junction for memory and logic design. Journal of Physics D, 47 (045001), December 2013.
[32]
L. Wanhammar. DSP integrated circuits. Academic press 1999.
[33]
D. Williamson. Arm cortex-a8: A high-performance processor for low-power applications. Unique Chips and Systems, page 79, 2007.
[34]
S.-Y. Wu. A new ferroelectric memory device, metal-ferroelectric-semiconductor transistor. IEEE TED, 21 (8):499–504, 1974.

Cited By

View all
  • (2025)Nonvolatile logic gate and full adder based on tri-terminal oxide resistive switching devicesMicroelectronic Engineering10.1016/j.mee.2024.112280295:COnline publication date: 2-Jan-2025
  • (2024)Analyzing Various Structural and Temperature Characteristics of Floating Gate Field Effect Transistors Applicable to Fine-Grain Logic-in-Memory DevicesMicromachines10.3390/mi1504045015:4(450)Online publication date: 27-Mar-2024
  • (2024)Memorable Logic Gate Based on Field Effect Oxide Resistive Switching Devices2024 IEEE International Conference on IC Design and Technology (ICICDT)10.1109/ICICDT63592.2024.10717650(1-3)Online publication date: 25-Sep-2024
  • Show More Cited By

Index Terms

  1. Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuits
        Index terms have been assigned to the content through auto-classification.

        Recommendations

        Comments

        Information & Contributors

        Information

        Published In

        cover image Guide Proceedings
        2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
        Nov 2016
        946 pages

        Publisher

        IEEE Press

        Publication History

        Published: 07 November 2016

        Permissions

        Request permissions for this article.

        Qualifiers

        • Research-article

        Contributors

        Other Metrics

        Bibliometrics & Citations

        Bibliometrics

        Article Metrics

        • Downloads (Last 12 months)0
        • Downloads (Last 6 weeks)0
        Reflects downloads up to 08 Mar 2025

        Other Metrics

        Citations

        Cited By

        View all
        • (2025)Nonvolatile logic gate and full adder based on tri-terminal oxide resistive switching devicesMicroelectronic Engineering10.1016/j.mee.2024.112280295:COnline publication date: 2-Jan-2025
        • (2024)Analyzing Various Structural and Temperature Characteristics of Floating Gate Field Effect Transistors Applicable to Fine-Grain Logic-in-Memory DevicesMicromachines10.3390/mi1504045015:4(450)Online publication date: 27-Mar-2024
        • (2024)Memorable Logic Gate Based on Field Effect Oxide Resistive Switching Devices2024 IEEE International Conference on IC Design and Technology (ICICDT)10.1109/ICICDT63592.2024.10717650(1-3)Online publication date: 25-Sep-2024
        • (2024)Challenges and recent advances in HfO2-based ferroelectric films for non-volatile memory applicationsChip10.1016/j.chip.2024.100101(100101)Online publication date: Jun-2024
        • (2024)Emerging Technologies for Memory-Centric ComputingDesign and Applications of Emerging Computer Systems10.1007/978-3-031-42478-6_1(3-29)Online publication date: 14-Jan-2024
        • (2024)Investigation on Artificial Intelligence Hardware Architecture Design Based on Logic‐in‐Memory Ferroelectric Fin Field‐Effect Transistor at Sub‐3nm Technology NodesAdvanced Intelligent Systems10.1002/aisy.2024003707:2Online publication date: 4-Sep-2024
        • (2023)Non Volatile Operators Emulation PlatformProceedings of the 18th ACM International Symposium on Nanoscale Architectures10.1145/3611315.3633252(1-6)Online publication date: 18-Dec-2023
        • (2023)FeFET based Logic-in-Memory design methodologies, tools and open challenges2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC57769.2023.10321901(1-6)Online publication date: 16-Oct-2023
        • (2023)SBCT-NoC: Ultra Low-Power and Reliable Simultaneous Bi-Directional Current-Mode Transceiver for Network-on-Chip InterconnectsIEEE Transactions on Nanotechnology10.1109/TNANO.2022.320531722(777-784)Online publication date: 2023
        • (2023)Effect of Floating Gate Insertion on the Analog States of Ferroelectric Field-Effect TransistorsIEEE Transactions on Electron Devices10.1109/TED.2022.322364070:1(349-353)Online publication date: Jan-2023
        • Show More Cited By

        View Options

        View options

        Figures

        Tables

        Media

        Share

        Share

        Share this Publication link

        Share on social media