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Generation and use of statistical timing macro-models considering slew and load variability

Published: 07 November 2016 Publication History

Abstract

Timing macro-modeling captures the timing characteristics of a circuit in a compact form for use in a hierarchical timing environment. At the same time, statistical timing provides coverage of the impact from variability sources with the goal of enabling higher chip yield. This paper presents an efficient and accurate method for generation and use of statistical timing macro-models. Results in a commercial timing analysis framework with non-separable statistical timing models demonstrate average performance improvements of 10× when using the model with less than 0.3 picosecond average and 5.5 picosecond maximum accuracy loss, respectively.

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  • (2020)Gate Sizing for Power-Delay Optimization at Transistor-level Monolithic 3D-Integrated Circuits2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS)10.1109/LASCAS45839.2020.9069042(1-4)Online publication date: Feb-2020

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        2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
        Nov 2016
        946 pages

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        Published: 07 November 2016

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        • (2020)Gate Sizing for Power-Delay Optimization at Transistor-level Monolithic 3D-Integrated Circuits2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS)10.1109/LASCAS45839.2020.9069042(1-4)Online publication date: Feb-2020

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