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View all- Zanelli JMetzler CReis R(2020)Gate Sizing for Power-Delay Optimization at Transistor-level Monolithic 3D-Integrated Circuits2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS)10.1109/LASCAS45839.2020.9069042(1-4)Online publication date: Feb-2020