Xingbo Wu
Fan Ni
Zili Shao
Song Jiang
ABSTRACT
As byte-addressable, high-density, and non-volatile memory (NVM) is around the corner to be equipped alongside the DRAM memory, issues on enabling the important key-value cache services, such as memcached, on the new storage medium must be addressed. While NVM allows data in a KV cache to survive power outage and system crash, in practice their integrity and accessibility depend on data consistency enforced during writes to NVM. Though techniques for enforcing the consistency, such as journaling, COW, or checkpointing, are available, they are often too expensive by frequently using CPU cache flushes to ensure crash consistency, leading to (much) reduced performance and excessively compromised NVM's lifetime.
In this paper we design and evaluate NVMcached, a KV cache for non-volatile byte-addressable memory that can significantly reduce use of flushes and minimize data loss by leveraging consistency-friendly data structures and batched space allocation and reclamation. Experiments show that NVMcached can improve its system throughput by up to 2.8x for write-intensive real-world workloads, compared to a non-volatile memcached.
- Amazon. ElastiCache. http://aws.amazon.com/elasticache/.Google Scholar
- B. Atikoglu, Y. Xu, E. Frachtenberg, S. Jiang, and M. Paleczny. Workload Analysis of a Large-scale Key-value Store. In Proceedings of the 12th ACM SIGMETRICS/PERFORMANCE Joint International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS '12, pages 53--64, New York, NY, USA, 2012. ACM. Google ScholarDigital Library
- S. Chen and Q. Jin. Persistent B+trees in Non-volatile Main Memory. Proc. VLDB Endow., 8(7):786--797, Feb. 2015. Google ScholarDigital Library
- J. Coburn, A. M. Caulfield, A. Akel, L. M. Grupp, R. K. Gupta, R. Jhala, and S. Swanson. NV-Heaps: Making Persistent Objects Fast and Safe with Next-generation, Non-volatile Memories. In Proceedings of the Sixteenth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS XVI, pages 105--118, New York, NY, USA, 2011. ACM. Google ScholarDigital Library
- J. Condit, E. B. Nightingale, C. Frost, E. Ipek, B. Lee, D. Burger, and D. Coetzee. Better I/O Through Byte-addressable, Persistent Memory. In Proceedings of the ACM SIGOPS 22nd Symposium on Operating Systems Principles, SOSP '09, pages 133--146, New York, NY, USA, 2009. ACM. Google ScholarDigital Library
- B. F. Cooper, A. Silberstein, E. Tam, R. Ramakrishnan, and R. Sears. Benchmarking Cloud Serving Systems with YCSB. In Proceedings of the 1st ACM Symposium on Cloud Computing, SoCC '10, pages 143--154, New York, NY, USA, 2010. ACM. Google ScholarDigital Library
- J. Evans. jemalloc. http://www.canonware.com/jemalloc/.Google Scholar
- B. Fan, D. G. Andersen, and M. Kaminsky. MemC3: Compact and Concurrent MemCache with Dumber Caching and Smarter Hashing. In Proceedings of the 10th USENIX Conference on Networked Systems Design and Implementation, NSDI'13, pages 371--384, Berkeley, CA, USA, 2013. USENIX Association. Google ScholarDigital Library
- S. Gao, B. He, and J. Xu. Real-Time In-Memory Checkpointing for Future Hybrid Memory Systems. In Proceedings of the 29th ACM on International Conference on Supercomputing, ICS '15, pages 263--272, New York, NY, USA, 2015. ACM. Google ScholarDigital Library
- S. Ghemawat and P. Menage. tcmalloc. http://goog-perftools.sourceforge.net/doc/tcmalloc.html.Google Scholar
- J. Huang, K. Schwan, and M. K. Qureshi. NVRAM-aware Logging in Transaction Systems. Proc. VLDB Endow., 8(4):389--400, Dec. 2014. Google ScholarDigital Library
- Intel Corporation. NVM Library. http://pmem.io/about/.Google Scholar
- Intel Corporation. 3D XPoint Unveiled - The Next Breakthrough in Memory Technology. http://goo.gl/JiilPt, 2015.Google Scholar
- Intel Corporation. Intel® 64 and IA-32 Architectures Software Developer Manuals. Number 253665-056US. September 2015.Google Scholar
- W.-H. Kim, J. Kim, W. Baek, B. Nam, and Y. Won. NVWAL: Exploiting NVRAM in Write-Ahead Logging. In Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS '16, pages 385--398, New York, NY, USA, 2016. ACM. Google ScholarDigital Library
- E. Kultursay, M. Kandemir, A. Sivasubramaniam, and O. Mutlu. Evaluating STT-RAM as an energy-efficient main memory alternative. In Performance Analysis of Systems and Software (ISPASS), 2013 IEEE International Symposium on, pages 256--267. IEEE, 2013.Google ScholarCross Ref
- D. Lea. A Memory Allocator. http://g.oswego.edu/dl/html/malloc.html.Google Scholar
- B. C. Lee, E. Ipek, O. Mutlu, and D. Burger. Architecting Phase Change Memory As a Scalable DRAM Alternative. In Proceedings of the 36th Annual International Symposium on Computer Architecture, ISCA '09, pages 2--13, New York, NY, USA, 2009. ACM. Google ScholarDigital Library
- C. Li and A. L. Cox. GD-Wheel: A Cost-aware Replacement Policy for Key-value Stores. In Proceedings of the Tenth European Conference on Computer Systems, EuroSys '15, pages 5:1--5:15, New York, NY, USA, 2015. ACM. Google ScholarDigital Library
- S. Li, H. Lim, V. W. Lee, J. H. Ahn, A. Kalia, M. Kaminsky, D. G. Andersen, O. Seongil, S. Lee, and P. Dubey. Architecting to Achieve a Billion Requests Per Second Throughput on a Single Key-value Store Server Platform. In Proceedings of the 42nd Annual International Symposium on Computer Architecture, ISCA '15, pages 476--488, New York, NY, USA, 2015. ACM. Google ScholarDigital Library
- I. Moraru, D. G. Andersen, M. Kaminsky, N. Tolia, P. Ranganathan, and N. Binkert. Consistent, Durable, and Safe Memory Management for Byte-addressable Non Volatile Main Memory. In Proceedings of the First ACM SIGOPS Conference on Timely Results in Operating Systems, TRIOS '13, pages 1:1--1:17, New York, NY, USA, 2013. ACM. Google ScholarDigital Library
- T. S. Pillai, V. Chidambaram, R. Alagappan, S. Al-Kiswany, A. C. Arpaci-Dusseau, and R. H. Arpaci-Dusseau. Crash Consistency. Queue, 13(7):20:20--20:28, July 2015. Google ScholarDigital Library
- D. Ralph and M. D. Stiles. Spin transfer torques. Journal of Magnetism and Magnetic Materials, 320(7):1190--1216, 2008.Google ScholarCross Ref
- J. Ren, J. Zhao, S. Khan, J. Choi, Y. Wu, and O. Mutlu. ThyNVM: Enabling Software-transparent Crash Consistency in Persistent Memory Systems. In Proceedings of the 48th International Symposium on Microarchitecture, MICRO-48, pages 672--685, New York, NY, USA, 2015. ACM. Google ScholarDigital Library
- S. M. Rumble, A. Kejriwal, and J. Ousterhout. Log-structured Memory for DRAM-based Storage. In Proceedings of the 12th USENIX Conference on File and Storage Technologies, FAST'14, pages 1--16, Berkeley, CA, USA, 2014. USENIX Association. Google ScholarDigital Library
- S. Venkataraman, N. Tolia, P. Ranganathan, and R. H. Campbell. Consistent and Durable Data Structures for Non-volatile Byte-addressable Memory. In Proceedings of the 9th USENIX Conference on File and Storage Technologies, FAST'11, pages 5--5, Berkeley, CA, USA, 2011. USENIX Association. Google ScholarDigital Library
- H. Volos, A. J. Tack, and M. M. Swift. Mnemosyne: Lightweight Persistent Memory. In Proceedings of the Sixteenth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS XVI, pages 91--104, New York, NY, USA, 2011. ACM. Google ScholarDigital Library
- G. Wang, Y. Yang, J.-H. Lee, V. Abramova, H. Fei, G. Ruan, E. L. Thomas, and J. M. Tour. Nanoporous Silicon Oxide Memory. Nano letters, 14(8):4694--4699, 2014.Google ScholarCross Ref
- Wikipedia. Memcached. https://en.wikipedia.org/wiki/Memcached.Google Scholar
- H. P. Wong, S. Raoux, S. Kim, J. Liang, J. P. Reifenberg, B. Rajendran, M. Asheghi, and K. E. Goodson. Phase change memory. Proceedings of the IEEE, 98(12):2201--2227, 2010.Google ScholarCross Ref
- X. Wu, Y. Xu, Z. Shao, and S. Jiang. LSM-trie: An LSM-tree-based Ultra-large Key-value Store for Small Data. In Proceedings of the 2015 USENIX Conference on Usenix Annual Technical Conference, USENIX ATC '15, pages 71--82, Berkeley, CA, USA, 2015. USENIX Association. Google ScholarDigital Library
- X. Wu, L. Zhang, Y. Wang, Y. Ren, M. Hack, and S. Jiang. zExpander: a Key-Value Cache with both High Performance and Fewer Misses. In Proceedings of the Ninth European Conference on Computer Systems, EuroSys '16, New York, NY, USA, 2016. ACM. Google ScholarDigital Library
- Y. Xu, E. Frachtenberg, and S. Jiang. Building a high-performance key-value cache as an energy-efficient appliance. Perform. Eval., 79:24--37, 2014.Google ScholarCross Ref
- J. Yang, Q. Wei, C. Chen, C. Wang, K. L. Yong, and B. He. NV-Tree: Reducing Consistency Cost for NVM-based Single Level Systems. In Proceedings of the 13th USENIX Conference on File and Storage Technologies, FAST'15, pages 167--181, Berkeley, CA, USA, 2015. USENIX Association. Google ScholarDigital Library
- Y. Zhang, G. Soundararajan, M. W. Storer, L. N. Bairavasundaram, S. Subbiah, A. C. Arpaci-Dusseau, and R. H. Arpaci-Dusseau. Warming Up Storage-Level Caches with Bonfire. In Presented as part of the 11th USENIX Conference on File and Storage Technologies (FAST 13), pages 59--72, San Jose, CA, 2013. USENIX. Google ScholarDigital Library
Recommendations
WOM-Code Solutions for Low Latency and High Endurance in Phase Change Memory
This paper describes a write-once-memory-code phase change memory (WOM-code PCM) architecture for next-generation non-volatile memory applications. Specifically, we address the long latency of the write operation in PCM—attributed to PCM SET—...
Design and Optimization of Large Size and Low Overhead Off-Chip Caches
Large off-chip L3 caches can significantly improve the performance of memory-intensive applications. However, conventional L3 SRAM caches are facing two issues as those applications require increasingly large caches. First, an SRAM cache has a limited ...
Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh
Spin-Torque Transfer RAM (STT-RAM) is a promising candidate for SRAM replacement because of its excellent features, such as fast read access, high density, low leakage power, and CMOS technology compatibility. However, wide adoption of STT-RAM as cache ...
Comments