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Very High Level Synthesis for image processing applications

Published: 12 September 2016 Publication History

Abstract

Since the recent 20 years, High Level Synthesis (HLS) has made significantly progresses. This technique greatly benefits the R&D productivity of the FPGA designs and helps for adding to the maintainability of the products by automating the C-to-RTL conversion. However, due to the high complexity and computational intensity, image processing designs usually necessitate a higher abstraction level than C-synthesis, and the current HLS tools do not have the ability of this kind. This paper presents a Very High Level Synthesis method which allows fast prototyping and verifying the FPGA designs in the Matlab environment. We build a heterogeneous design flow by using currently-available tool kits for verifying the proposed approach and evaluated it within two real-life applications. Experiment results demonstrate that it can effectively reduce the complexity of the design and give play to the advantages of FPGAs related to the other devices.

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Cited By

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  • (2023)A RTL Implementation of Heterogeneous Machine Learning Network for French Computer Assisted Pronunciation TrainingApplied Sciences10.3390/app1310583513:10(5835)Online publication date: 9-May-2023
  • (2019)Resource‐efficient FPGA implementation of perspective transformation for bird's eye view generation using high‐level synthesis frameworkIET Circuits, Devices & Systems10.1049/iet-cds.2018.526313:6(756-762)Online publication date: 11-Jul-2019
  • (2017)Fast FPGA prototyping for real-time image processing with very high-level synthesisJournal of Real-Time Image Processing10.1007/s11554-017-0688-1Online publication date: 11-Apr-2017
  1. Very High Level Synthesis for image processing applications

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    cover image ACM Other conferences
    ICDSC '16: Proceedings of the 10th International Conference on Distributed Smart Camera
    September 2016
    242 pages
    ISBN:9781450347860
    DOI:10.1145/2967413
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 12 September 2016

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    Author Tags

    1. Design Space Exploration
    2. Electronic Design Automating
    3. Embedded System
    4. FPGA
    5. High-Level Synthesis
    6. Image Processing
    7. Programming Linguistic
    8. Software/Hardware Co-design

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    Overall Acceptance Rate 92 of 117 submissions, 79%

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    Cited By

    View all
    • (2023)A RTL Implementation of Heterogeneous Machine Learning Network for French Computer Assisted Pronunciation TrainingApplied Sciences10.3390/app1310583513:10(5835)Online publication date: 9-May-2023
    • (2019)Resource‐efficient FPGA implementation of perspective transformation for bird's eye view generation using high‐level synthesis frameworkIET Circuits, Devices & Systems10.1049/iet-cds.2018.526313:6(756-762)Online publication date: 11-Jul-2019
    • (2017)Fast FPGA prototyping for real-time image processing with very high-level synthesisJournal of Real-Time Image Processing10.1007/s11554-017-0688-1Online publication date: 11-Apr-2017

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