Cited By
View all- Ansari MCho S(2021)Performance Improvement of 1T DRAM by Raised Source and Drain EngineeringIEEE Transactions on Electron Devices10.1109/TED.2021.305695268:4(1577-1584)Online publication date: Apr-2021
Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes
Article No.: 23, Pages 1 - 22
Abstract
Extending double-gate FinFET scaling to sub-10nm technology regime requires device-engineering techniques for countering the rise of direct source to drain tunneling (DSDT), edge direct tunneling (EDT) and short channel effects (SCE) that degrade FinFET I-V characteristics. Symmetric underlap is effective for eliminating EDT, diminishing DSDT, and lowering the fringe component of gate capacitance. However, excessive symmetric underlap also lowers the on-current, which is mainly due to thermionic emission. In this work, it is demonstrated that at sub-10nm node, asymmetric underlapped FinFETs with slightly longer underlap toward drain side than source side are superior to symmetric underlapped FinFETs due to further improvement in Ion/Ioff and reduction in gate-to-drain capacitance. Using quantum mechanical device simulations, FinFETs with various degrees of underlap have been analyzed for improvement in I-V characteristics. A FinFET model for circuit simulations has been constructed that captures the major sub-10nm leakage components, namely, thermionic emission, DSDT, EDT, direct gate oxide tunneling and its associated components. By simulating a 10-stage NAND circuit and a LEON3 processor with interconnect parasitics using these devices, it is shown that asymmetric underlap instead of symmetric underlap in sub-10nm FinFETs can offer lower energy consumption with improved performance for near-threshold logic and higher energy-efficiency for super-threshold logic operation.
References
[1]
Aditya Bansal, Bipul C. Paul, and Kaushik Roy. 2005. Modeling and optimization of fringe capacitance of nanoscale DGMOS devices. IEEE Trans. Electron Dev. 52, 2, 256--262.
[2]
Mark Bohr. 2014. 14nm process technology: Opening new horizons. Intel Developer Forum (IDF’14).
[3]
P. Carpena, J. A. Lopez Villanueva, and V. Gasparian. 1998. Energy dependence of the effective mass in the envelope function approximation. Physica B: Condensed Matter. 253, 3--4, 242--249.
[4]
Leroy Chang, Yang-Kyu Choi, Daewon Ha, Pushkar Ranade, Shiying Xiong, Jeffrey Bokor, Chenming Hu, and Tsu-Jae King. 2003. Extremely scaled Silicon nano-CMOS devices. Proc. IEEE. 91, 11, 1860--1873.
[5]
Yang-Kyu Choi, Daewon Ha, Tsu-Jae King, and Jeffrey Bokor. 2003. Investigation of gate-induced drain leakage (GIDL) current in thin body devices: Single-gate ultra-thin body, symmetrical double-gate and asymmetrical double-gate MOSFETs. Japan. J. Appl. Phys. 42, 4B, 2073--2076.
[6]
Supriyo Datta. 2002. The non-equilibrium Green's function (NEGF) formalism: An elementary introduction. In IEDM Technical Digest (IEDM’02), 703--706.
[7]
Ronald Dreslinski, Michael Wieckowski, David Blaauw, Dennis Sylvester, and Trevor Mudge. 2009. Near threshold computing: Overcoming performance degradation from aggressive voltage scaling. In Workshop of Energy-Efficient Design (WEED’09), 44--49.
[8]
Gaisler. 2015: http://www.gaisler.com/index.php/products/processors/leon3
[9]
Ashish Goel, Sumeet Kumar Gupta, and Kaushik Roy. 2011. Asymmetric drain spacer extension (ADSE) FinFETs for low-power and robust SRAMs. IEEE Trans. Electron Dev. 58, 2, 296--308.
[10]
Akkala Arun Goud, Sumeet Kumar Gupta, Sri Harsha Choday, and Kaushik Roy. 2013. Atomistic tight-binding based evaluation of impact of gate underlap on source to drain tunneling in 5nm gate length Si FinFETs. In IEEE Device Research Conference Tech. Digest (DRC’13), 51, 52.
[11]
Akkala Arun Goud, Rangharajan Venkatesan, Anand Raghunathan, and Kaushik Roy. 2015. Asymmetric underlapped FinFET based robust SRAM design at 7nm. In IEEE Design Automation and Test in Europe Conference (DATE’15), 659--664.
[12]
Sumeet Kumar Gupta, Woo-Suhl Cho, Arun Goud Akkala, Karthik Yogendra, and Kaushik Roy. 2013. Design space exploration of FinFETs in sub-10nm technologies for energy-efficient near-threshold circuits. In IEEE Device Research Conference Tech. Digest (DRC’13), 117, 118.
[13]
Ximeng Guan, Donghyun Kim, Krishna Saraswat, and Philip Wong. 2011. Analytical approximation of complex band structures for band-to-band tunneling models. In IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD’11), 267--270.
[14]
ITRS. 2011: http://www.itrs.net/Links/2011ITRS/Home2011.htm.
[15]
Hisao Kawaura, Toshitsugu Sakamoto, and Toshio Baba. 2000. Observation of source-to-drain direct tunneling current in 8nm gate electrically variable shallow junction metal-oxide-semiconductor field-effect transistors. Applied Physics Letters. 76, 25, 3810--3812.
[16]
Jakub Kedzierski, Meikei Ieong, Edward Nowak, Thomas Kanarsky, Ying Zhang, Ronnen Roy, Diane Boyd, David Fried, and H. S. Philip Wong. 2003. Extension and source/drain design for high-performance FinFET Devices. In IEEE Transactions on Electron Devices. 50, 4, 952--958.
[17]
Hasanur R. Khan, Denis Mamaluy, and Dragica Vasileska. 2007. Quantum transport simulation of experimentally fabricated nano-FinFET. IEEE Transactions on Electron Devices. 54, 4, 784--796.
[18]
Pranita Kerber, Qintao Zhang, Siyuranga Koswatta, and Andres Bryant. 2013. GIDL in doped and undoped FinFET devices for low-leakage applications. IEEE Electron Device Letters. 34, 1, 6--8.
[19]
Tillmann C. Kubis, Michael Povolotskyi, Jean Michel Sellier, James Fonseca, and Gerhard Klimeck. 2012. NEMO5 overview presentation.
[20]
LEON3 Data Sheet. 2015: http://www.actel.com/ipdocs/LEON3_DS.pdf.
[21]
Dejan Markovic, Cheng C. Wang, Louis P. Alarcon, Tsung-Te Liu, and Jan M. Rabaey. 2010. Ultralow-power design in near-threshold region. Proc. IEEE. 98, 2, 237--252.
[22]
Saumitra Mehrotra, SungGeun Kim, Tillmann Kubis, Michael Povolotskyi, Mark Lundstrom, and Gerhard Klimeck. 2013. Engineering nanowire n-MOSFETs at Lg<8nm. IEEE Trans. Electron Dev. 60, 7, 2171--2177.
[23]
Farshad Moradi, Sumeet Kumar Gupta, Georgios Panagopoulos, Dag T. Wisland, Hamid Mahmoodi, and Kaushik Roy. 2011. Asymmetrically doped FinFETs for low-power robust SRAMs. In IEEE Trans. Electron Dev. 58, 12, 4241--4249.
[24]
Samik Mukherjee, Abhijeet Paul, Neophytos Neophytou, et al. 2015. Bandstructure lab.
[25]
Saibal Mukhopadhyay, Cassandra Neau, Tamir Cakici, Amit Agarwal, Chris Kim, and Kaushik Roy. 2003. Gate leakage reduction for scaled devices using transistor stacking. IEEE Trans. Very Large-Scale Integ. Syst. 11, 4, 716--730.
[26]
Neophytos Neophytou and Hans Kosina, 2011. Atomistic simulations of low-field mobility in Si nanowires: Influence of confinement and orientation. Phys. Rev. B 84, 085313, 1--15.
[27]
Arijit Raychowdhury, Charles Augustine, Yunfei Gao, Mark Lundstrom, and Kaushik Roy. 2014. PETE: Purdue emerging technology evaluator.
[28]
Zhibin Ren, Venugopal Rao, Supriyo Datta, Mark Lundstrom, Dejan Jovanovic, and Jerry Fossum. 2000. The ballistic nanotransistor: A simulation study. In Proceedings of the International Electron Devices Meeting (IEDM’00), 715--718.
[29]
Klaus Schuegraf and Chenming Hu. 1994. Hole injection SiO2 breakdown model for very low voltage lifetime extrapolation. IEEE Trans. Electron Dev. 41, 5, 761--767.
[30]
M. Staedele. 2002. Influence of source-drain tunneling on the subthreshold behavior of sub-10nm double-gate MOSFETs. In IEEE European Solid State Device Research Conference (ESSDERC’02), 135--138.
[31]
Reinaldo A. Vega, Kevin Liu, and Tsu-Jae King. 2009. Dopant-segregated Schottky source/drain double-gate MOSFET design in the direct source-to-drain tunneling regime. IEEE Trans. Electron Dev. 56, 9, 2016--2026.
[32]
S. K. Vishwakarma, V. Komal Kumar, A. K. Saxena, and S. Dasgupta. 2011. Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlNx) symmetric double gate MOSFET. Microelectron. J. 42, 5, 688--692.
[33]
Jing Wang and Mark Lundstrom. 2002. Does source-to-drain tunneling limit the ultimate scaling of MOSFETs? In IEDM Technical Digest (IEDM’02), 707--710.
[34]
Jing Wang, Anisur Rahman, Avik Ghosh, Gerhard Klimeck, and Mark Lundstrom. 2005. On the validity of the parabolic effective mass approximation for the I-V calculation of Silicon nanowire transistors. IEEE Transact. Electron Dev. 52, 7, 1589--1595.
[35]
Qing Xie, Xue Lin, Yanzhi Wang, Mohammad Dousti, Alireza Shafaei, Majid Gol, and Massoud Pedram. 2014. 5nm FinFET standard cell library optimization and circuit synthesis in near- and super-threshold voltage regimes. In IEEE Computer Society Symposium on VLSI (ISVLSI’14), 424--429.
[36]
Yee-Chia Yeo, Tsu-Jae King, and Chenming Hu. 2002. Direct tunneling leakage current and scalability of alternative gate dielectrics. Appl. Phys. Lett. 81, 11, 2091--2093.
[37]
Hui Zhao, Yee-Chia Yeo, Subhash C. Rustagi, and Ganesh Shankar Samudra. 2008. Analysis of the effects of fringing electric field on FinFET device performance and structural optimization using 3-D Simulation. IEEE Trans. Electron Dev. 55, 5, 1177--1184.
Index Terms
- Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes
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Publication History
Published: 02 November 2016
Accepted: 01 June 2016
Revised: 01 April 2016
Received: 01 September 2015
Published in JETC Volume 13, Issue 2
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View all- Ansari MCho S(2021)Performance Improvement of 1T DRAM by Raised Source and Drain EngineeringIEEE Transactions on Electron Devices10.1109/TED.2021.305695268:4(1577-1584)Online publication date: Apr-2021
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