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A Designing of Random Access Memory Using Different IO Standard Technology

Published: 06 July 2016 Publication History

Abstract

In this work, we proposed simulation of RAM memory using different IO Standard technologies on 28nm feature size FPGA. LVTTL and Mobile-DDR IO standard is used for designing RAM circuit, power consumption by this Memory has been calculated by applying two different technologies i.e. Mobile-DDR and Low Voltage Transistor- Transistor Logic. Both IO Standards are compared with each other to find out the most power efficient one. We validated our circuit with different IO Standards and on Different frequency range to obtain a most power efficient circuit. In our work, there is 28.05% power reduction when LVTTL is replaced with Mobile-DDR on 1 GHz frequency and 47.93% power reduction at 4GHz operating frequency. To design this energy efficient memory circuit, we are using Verilog as HDL, Xilinx ISE 14.2 simulator with Artix-7 FPGA.

References

[1]
Ravinder kaur, Jagdish kumar, Sumita Nagah, Bishwajeet Pandey, Kavita Goswami, "IO Standard Based Low Power Memory Design and Implementation on FPGA", 2nd International Conference on "Computing for Sustainable Global Development", 11th-13th March, 2015.
[2]
Weis, L Loi, L. Benini and N. Wehn, "An Energy Efficient DRAM Subsystem for 3D integrated SoCs", Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012. IEEE, 2012.
[3]
Sweety, Bishwajeet Pandey, Tanesh Kumar, Teerath Das, "Design of Power Optimized Memory Circuit Using High Speed Transreceiver Logic 10 Standard on 28nm Field Programmable Gate Array", International Conference on Reliability, Optimization and Information Technology - ICROIT 2014, India.
[4]
WEI WEI, KAZUTERU NAMBA, FABRIZIO LOMBARDI, "Extending Non- Volatile Operation to DRAM cells", IEEE Access November 1, 2013.
[5]
Xiaowei Han*, Stanley L. Chen, Lihua Wu, Yan Zhao, Yan Li "Design and Verification of Distributed RAM Using Look-Up Tables in an SOI-Based FPGA", Solid-State and Integrated Circuit Technology (ICSICT),10th IEEE International Conference on. IEEE, 2010.
[6]
Gaurav verma, Aditi Moudgil, Kanika Garg, Bishwajeet Pandey, "Thermal and Power Aware Internet of Things Enable RAM Design on FPGA", 2nd International Conference on "Computing for Sustainable Global Development", 11th-13th March, 2015.
[7]
Dev, M., Baghel, D., Pattanaik, M., Shukla, A., "Clock Gated Low Power Sequential Circuit Design", IEEE Conference on Information and Communication Technologies(ICT), 11-12 April, 2013.
[8]
Kaliamurthy, S., Sowmmiya, U., "VHDL Design of FPGA Arithmetic Processor" Global International Journal of Researches in Electronics and Communication Engineering vol. 11, no., Nov. 2011.
[9]
Pandey, B., and Pattanaik, M., "Clock Gating Aware Low Power ALU Design and Implementation on FPGA", 2nd International Conference on Network and Computer Science (ICNCS), Singapore, April 1-2, 2013.
[10]
L.-Y. Huang, "ReRAM-based 4T2R Nonvolatile TCAM with 7x NVM-Stress Reduction, and 4x Improvement in Speed-Word Length-Capacity for Normally-Off Instant-On Filter-Based Search Engines Used in Big-Data Processing", IEEE Symp. VLSI Circuits, pp. 99--100
[11]
N. Verma and A. P. Chandrakasan, "A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy", IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 141--149, 2008.
[12]
C. B. Kushwah, D. Dwivedi and N. Sathisha, "8T based SRAM cell and related method U.S. Patent IN920130 218 US1", 2013.
[13]
E. Seevinck, F. J. List and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells", IEEE J. Solid-State Circuits, vol. 22, no. 5, pp. 748--754, 1987.
[14]
M. Khayatzadeh and Y. Lian, "Average-8T differential-sensing subthreshold SRAM with bit interleaving and 1k bits per bitline", IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 5, pp. 971--982, 2014.
[15]
Gaurav verma, Aditi Moudgil, Kanika Garg, Bishwajeet Pandey, "Thermal and Power Aware Internet of Things Enable RAM Design on FPGA", 2nd International Conference on "Computing for Sustainable Global Development", 11th-13th March, 2015.

Cited By

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  • (2022)Optimizing Leakage Current and Fluctuations at Ground Rail in 1-bit 8T Full Adder Circuit Using Various MTCMOS Techniques2022 4th International Conference on Inventive Research in Computing Applications (ICIRCA)10.1109/ICIRCA54612.2022.9985706(174-179)Online publication date: 21-Sep-2022

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cover image ACM Other conferences
ICCCNT '16: Proceedings of the 7th International Conference on Computing Communication and Networking Technologies
July 2016
262 pages
ISBN:9781450341790
DOI:10.1145/2967878
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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  • University of North Texas: University of North Texas

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 July 2016

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Author Tags

  1. FPGA
  2. IO Standard
  3. LVTTL
  4. Low Power
  5. Mobile-DDR
  6. RAM

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  • Research
  • Refereed limited

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ICCCNT '16

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ICCCNT '16 Paper Acceptance Rate 48 of 101 submissions, 48%;
Overall Acceptance Rate 48 of 101 submissions, 48%

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View all
  • (2022)Optimizing Leakage Current and Fluctuations at Ground Rail in 1-bit 8T Full Adder Circuit Using Various MTCMOS Techniques2022 4th International Conference on Inventive Research in Computing Applications (ICIRCA)10.1109/ICIRCA54612.2022.9985706(174-179)Online publication date: 21-Sep-2022

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