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POSTER: An Optimization of Dataflow Architectures for Scientific Applications

Published: 11 September 2016 Publication History

Abstract

Dataflow computing is proved to be promising in high-performance computing. However, traditional dataflow architectures are general-purpose and not efficient enough when dealing with typical scientific applications due to low utilization of function units. In this paper, we propose an optimization of dataflow architectures for scientific applications. The optimization introduces a request for operands mechanism and a topology-based instruction mapping algorithm to improve the efficiency of dataflow architectures. Experimental results show that the request for operands optimization achieves a 4.6% average performance improvement over the traditional dataflow architectures and the TBIM algorithm achieves a 2.28x and a 1.98x average performance improvement over SPDI and SPS algorithm respectively.

References

[1]
H. Fu, L. Gan, R. G. Clapp, H. Ruan, O. Pell, O. Mencer, M. Flynn, X. Huang and G. Yang. Scaling reverse time migration performance through reconfigurable dataflow engines. IEEE Micro, 34(1): 30--40, 2014.
[2]
D. Burger, S. W. Keckler, K. S. McKinley, M. Dahlin, L. K. John, C. Lin, C. R. Moore, J. Burrill, R. G. McDonald, W. Yoder and the TRIPS Team. Scaling to the end of silicon with EDGE architectures. IEEE Computer, 37(7): 44--55, 2004.
[3]
X. Ye, D. Fan, N. Sun, S. Tang, M. Zhang and H. Zhang. SimICT: A fast and flexible framework for performance and power evaluation of large-scale architecture. In Proceedings of the IEEE International Symposium on Low Power Electronics and Design, pages 273--278, 2013.
[4]
R. Nagarajan, S. K. Kushwaha, D. Burger, K. S. McKinley, C. Lin and S. W. Keckler. Static placement, dynamic issue (SPDI) scheduling for EDGE architectures. In Proceedings of the 13th International Conference on Parallel Achitecture and Compilation Techniques, pages 74--84, 2004.
[5]
K. E. Coons, X. Chen, S. K. Kushwaha, D. Burger and K. S. McKinley. A spatial path scheduling algorithm for EDGE architectures. In Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 129--140, 2006.

Cited By

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  • (2023)DFGC: DFG-aware NoC Control based on Time Stamp Prediction for Dataflow Architecture2023 IEEE 41st International Conference on Computer Design (ICCD)10.1109/ICCD58817.2023.00071(432-439)Online publication date: 6-Nov-2023
  • (2019)A Sharing Path Awareness Scheduling Algorithm for Dataflow Architecture2019 IEEE 21st International Conference on High Performance Computing and Communications; IEEE 17th International Conference on Smart City; IEEE 5th International Conference on Data Science and Systems (HPCC/SmartCity/DSS)10.1109/HPCC/SmartCity/DSS.2019.00017(9-18)Online publication date: Aug-2019
  • (2019)Simulation of Nodes and Blocks of Matching Processor of the Parallel Dataflow Computing System “Buran”2019 IEEE East-West Design & Test Symposium (EWDTS)10.1109/EWDTS.2019.8884376(1-5)Online publication date: Sep-2019
  • Show More Cited By

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  1. POSTER: An Optimization of Dataflow Architectures for Scientific Applications

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    Published In

    cover image ACM Conferences
    PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and Compilation
    September 2016
    474 pages
    ISBN:9781450341219
    DOI:10.1145/2967938
    Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 11 September 2016

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    Author Tags

    1. dataflow computing
    2. high-performance computing
    3. request for operands
    4. topology-based instruction mapping

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    PACT '16
    Sponsor:
    • IFIP WG 10.3
    • IEEE TCCA
    • SIGARCH
    • IEEE CS TCPP

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    PACT '16 Paper Acceptance Rate 31 of 119 submissions, 26%;
    Overall Acceptance Rate 121 of 471 submissions, 26%

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    Cited By

    View all
    • (2023)DFGC: DFG-aware NoC Control based on Time Stamp Prediction for Dataflow Architecture2023 IEEE 41st International Conference on Computer Design (ICCD)10.1109/ICCD58817.2023.00071(432-439)Online publication date: 6-Nov-2023
    • (2019)A Sharing Path Awareness Scheduling Algorithm for Dataflow Architecture2019 IEEE 21st International Conference on High Performance Computing and Communications; IEEE 17th International Conference on Smart City; IEEE 5th International Conference on Data Science and Systems (HPCC/SmartCity/DSS)10.1109/HPCC/SmartCity/DSS.2019.00017(9-18)Online publication date: Aug-2019
    • (2019)Simulation of Nodes and Blocks of Matching Processor of the Parallel Dataflow Computing System “Buran”2019 IEEE East-West Design & Test Symposium (EWDTS)10.1109/EWDTS.2019.8884376(1-5)Online publication date: Sep-2019
    • (2018)Optimizing the Efficiency of Data Transfer in Dataflow Architectures2018 IEEE 20th International Conference on High Performance Computing and Communications; IEEE 16th International Conference on Smart City; IEEE 4th International Conference on Data Science and Systems (HPCC/SmartCity/DSS)10.1109/HPCC/SmartCity/DSS.2018.00050(140-149)Online publication date: Jun-2018
    • (2018)Global Distributed Associative Environment - Evolution of Parallel Dataflow Computing System “Buran”2018 IEEE East-West Design & Test Symposium (EWDTS)10.1109/EWDTS.2018.8524849(1-5)Online publication date: Sep-2018

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