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Energy and timing aware synchronous programming
The synchronous paradigm is widely used for the design of safety critical systems. Such systems, especially in the medical devices domain, must meet strict timing requirements while also ensuring long battery life. As a consequence, they are subject to ...
Lessons learned on assumptions and scalability with time-aware instrumentation
Software instrumentation is a key technique in many stages of the development process. Instrumentation is particularly important for profiling, debugging, performance evaluation, and security analysis of real-time and embedded systems. Unfortunately, ...
Flexible support for time and costs in scenario-aware dataflow
Scenario-aware dataflow is a formalism to model modern dynamic embedded applications whose behaviour is heavily dependent on input data or the operational environment. Key behavioural aspects are the execution times and energy consumption of a system's ...
Making DDS really real-time with openflow
An increasing amount of distributed real-time systems and other critical infrastructure now rely on Data Distribution Service (DDS) middleware for timely dissementation of data between system nodes. While DDS has been designed specifically for use in ...
Exploring the performance of ROS2
Middleware for robotics development must meet demanding requirements in real-time distributed embedded systems. The Robot Operating System (ROS), open-source middleware, has been widely used for robotics applications. However, the ROS is not suitable ...
Locally optimal reach set over-approximation for nonlinear systems
Safety verification of embedded systems modeled as hybrid systems can be scaled up by employing simulation-guided reach set over-approximation techniques. Existing methods are either applicable to only restricted classes of systems, overly conservative, ...
Underminer: a framework for automatically identifying non-converging behaviors in black box system models
Evaluation of industrial embedded control system designs is a time-consuming and imperfect process. While an ideal process would apply a formal verification technique such as model checking or theorem proving, these techniques do not scale to industrial ...
Robust controller synthesis of switched systems using counterexample guided framework
We investigate the problem of synthesizing robust controllers that ensure that the closed loop satisfies an input reach-while-stay specification, wherein all trajectories starting from some initial set I, eventually reach a specified goal set G, while ...
An algorithmic approach to global asymptotic stability verification of hybrid systems
In this paper, we present an algorithmic approach to global asymptotic stability (GAS) verification of hybrid systems. Our broad approach consists of reducing the GAS verification to the verification of a region stability (RS) analysis problem and an ...
Verifying cyber-physical systems by combining software model checking with hybrid systems reachability
Cyber-physical systems (CPS) span the communication, computation and control domains. Creating a single, complete, and detailed model of a CPS is not only difficult, but, in terms of verification, probably not useful; current verification algorithms are ...
Darboux-type barrier certificates for safety verification of nonlinear hybrid systems
Benefit from less computational difficulty, barrier certificate based method has attracted much attention in safety verification of hybrid systems. Barrier certificates are inherent existences of a hybrid system and may have different types. A set of ...
A flattened hierarchical scheduler for real-time virtualization
Migrating legacy real-time software stacks to newer hardware platforms can be achieved with virtualization which allows several software stacks to run on a single machine. Existing solutions guarantee that deadlines of virtualized real-time systems are ...
RMC: an integrated runtime system for adaptive many-core computing
Many-core computing has surfaced as a promising solution to satisfy the rapidly increasing computational needs for various areas ranging from embedded to datacenter computing. However, when allocated with an excessive number of cores, multithreaded ...
Automatic HAL generation for embedded multiprocessor systems
Automated hardware design flows considerably speed up the development of embedded systems and are a useful asset during architecture exploration phase. However, any existing software has to be adapted for every new system. In this work we will ...
Real-time cache management for multi-core virtualization
Real-time virtualization techniques have been investigated with the primary goal of consolidating multiple real-time systems onto a single hardware platform while ensuring timing predictability. However, a shared last-level cache (LLC) on recent multi-...
Cache-related preemption delay analysis for multi-level inclusive caches
Cache-related preemption delay (CRPD) analysis is crucial when designing embedded control systems that employ preemptive scheduling. CRPD analysis for single-level caches has been studied extensively based on useful cache blocks (UCBs). As high-...
Modular deductive verification of sampled-data systems
Unsafe behavior of cyber-physical systems can have disastrous consequences, motivating the need for formal verification of these kinds of systems. Deductive verification in a proof assistant such as Coq is a promising technique for this verification ...
The SMT-based automatic road network generation in vehicle simulation environment
Vehicle simulators are widely used to test the correctness of vehicle control algorithms. It is important to create a virtual road environment in a way that the vehicle algorithm can be tested under various circumstances that may happen in the real ...
PCFIRE: towards provable <u>p</u>reventative <u>c</u>ontrol-<u>f</u>low <u>i</u>ntegrity enforcement for <u>r</u>ealistic <u>e</u>mbedded software
Control-Flow Integrity (CFI) is an important safety property of software, particularly in embedded and safety-critical systems, where CFI violations have led to patient deaths and can render cars remotely controllable by attackers. Previous techniques ...
A refinement theory for timed-dataflow analysis with support for reordering
Real-time stream processing applications executed on embedded multiprocessor systems often have strict throughput and latency constraints. Violating these constraints is undesired and temporal analysis methods are therefore used to prevent such ...
I/O scheduling with mapping cache awareness for flash based storage systems
NAND flash memory has been the default storage component in mobile systems. One of the key technologies for flash management is the address mapping scheme between logical addresses and physical addresses, which deals with the inability of in-place-...
The design of an efficient swap mechanism for hybrid DRAM-NVM systems
Non-Volatile Memory (NVM) is becoming an attractive candidate to be the swap area in embedded systems for its near-DRAM speed, low energy consumption, high density, and byte-addressability. Swapping data from DRAM out to NVM, however, can cause large ...
A fast, lightweight, and reliable file system for wireless sensor networks
Sensor nodes are increasingly used in critical applications. A file storage system that is fast, lightweight, and reliable across device failures is important to safeguard the data that these devices record. A fast and lightweight file system should ...
Schedulability analysis of mixed-criticality systems with multiple frequency specifications
In mixed-criticality systems functionalities of different criticalities, that need to have their correctness validated to different levels of assurance, co-exist upon a shared platform. Multiple specifications at differing levels of assurance may be ...
On-the-fly fast overrun budgeting for mixed-criticality systems
In mixed-criticality scheduling, the widely assumed mode-switch scheme assumes that both high- and low-criticality tasks are schedulable when no tasks overrun (normal mode) and all high-criticality tasks are schedulable even when they overrun (critical ...
Synthesizing time-triggered schedules for switched networks with faulty links
Time-triggered (TT) switched networks are a deterministic communication infrastructure used by real-time distributed embedded systems. These networks rely on the notion of globally discretized time (i.e. time slots) and a static TT schedule that ...
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Acceptance Rates
Year | Submitted | Accepted | Rate |
---|---|---|---|
EMSOFT '13 | 97 | 27 | 28% |
EMSOFT '09 | 106 | 33 | 31% |
Overall | 203 | 60 | 30% |