skip to main content
10.1145/2984393.2984410acmotherconferencesArticle/Chapter ViewAbstractPublication Pagesseeda-cecnsmConference Proceedingsconference-collections
research-article

Enhanced Tetris Legalization

Published: 25 September 2016 Publication History

Abstract

Legalization and detailed placement methods for standard cell designs, are two of the most notable topics in current VLSI research. Being the final steps in a classic placement procedure they must be efficient in terms of the delay overhead they introduce to the overall design flow and the quality of the final solution. In this paper we present a combined solution of the aforementioned steps, based on Tetris a particular simple and fast legalization algorithm, that produces considerable results taking into account the tradeoff between total wirelength, total cell displacement and runtime.

References

[1]
Brenner, U. and Vygen, J. 2006. Legalizing a placement with minimum total movement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 23, 12 (Nov. 2006), 1597--1613. DOI=http://dx.doi.org/10.1109/TCAD.2004.836733
[2]
Hill, D. 2002. Method and system for high speed detailed placement of cells within an integrated circuit design. US 6370673 B1. 2002.
[3]
Kahng, A. B., Markov, I. L., and Reda, S. 2004. On legalization of row-based placements. In Proceedings of the 14th ACM Great Lakes Symposium on VLSI (Boston, USA, April 26-28, 2004). GLSVLSI '04. ACM, New York, NY, USA, 214--219. DOI=http://dx.doi.org/10.1145/988952.989004
[4]
Kleinhans, J. M., Sigl, G., Johannes, F. M., and Antreich K. J. 1991. GORDIAN: VLSI placement by quadratic programming and slicing optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 10, 3 (Mar. 1991), 356--365. DOI=http://dx.doi.org/10.1109/43.67789
[5]
Koziri, M. and Eleftheriadis, A. 2010. Joint quantizer optimization for scalable coding. In Proceedings of the IEEE International Conference on Image Processing. (Hong Kong, Sep 26-29, 2010). ICIP'10. 1281--1284. DOI=http://dx.doi.org/10.1109/ICIP.2010.5653282
[6]
Koziri, M., Zacharis, D., Katsavounidis, I., and N. Bellas. 2011. Implementation of the AVS video decoder on a heterogeneous dual-core SIMD processor. IEEE Transactions on Consumer Electronics. 57,2 (May 2011), 673--681. DOI=http://dx.doi.org/10.1109/TCE.2011.5955207
[7]
Luo, T., Ren, H., Alpert, C. J. and Pan, D. Z. 2005. Computational geometry based placement migration. In Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design. ICCAD '05. IEEE Computer Society, Washington, DC, USA, 41--47.
[8]
Oikonomou, P., Loukopoulos, T., Dadaliaris, A.N., Koziri, M.G., and Stamoulis, G.I. 2015. On formulating and tackling integrated circuit placement as a scheduling problem. In Proceedings of the 19th Panhellenic Conference on Informatics (Athens, Greece, Oct 01-03, 2015). PCI '15. ACM, New York, NY, USA, 86--91. DOI=http://dx.doi.org/10.1145/2801948.2801965
[9]
Puget, J. C., Flach, G., Reis, R. and Johann, M. 2015. Jezz: An effective legalization algorithm for minimum displacement. In Proceedings of the 28th Symposium on Integrated Circuits and Systems Design (Salvador, Brazil, August 31-September 4, 2015). SBCCI '15. ACM, New York, NY, USA, 1--5. DOI=http://dx.doi.org/10.1145/2800986.2801013
[10]
Spindler, P., Schlichtmann, U., and Johannes, F. M. 2008. Abacus: fast legalization of standard cell circuits with minimal movement. In Proceedings of the 2008 International Symposium on Physical Design (Portland, USA, April 13 -16, 2008). ISPD '08. ACM, New York, NY, USA, 47--53. DOI=http://dx.doi.org/10.1145/1353629.1353640
[11]
Tziritas, N., Loukopoulos, T., Khan, S. U., and Xu, C. Z. 2015. Distributed Algorithms for the Operator Placement Problem. IEEE Transactions on Computational Social Systems. 2,4 (Dec. 2015), 182--196. DOI=http://dx.doi.org/10.1109/TCSS.2016.2519503
[12]
Viswanathan, N., Pan, M., and Chu, C. 2007. FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control. In Proceedings of the 2007 Asia and South Pacific Design Automation Conference. (Yokohama, Japan, Jan 23-26 2007). ASP-DAC '07. IEEE Computer Society, Washington, DC, USA, 135--140. DOI=http://dx.doi.org/10.1109/ASPDAC.2007.357975.

Cited By

View all

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Other conferences
SEEDA-CECNSM '16: Proceedings of the SouthEast European Design Automation, Computer Engineering, Computer Networks and Social Media Conference
September 2016
126 pages
ISBN:9781450348102
DOI:10.1145/2984393
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 25 September 2016

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. detailed placement
  2. legalization
  3. standard cell placement

Qualifiers

  • Research-article
  • Research
  • Refereed limited

Conference

SEEDA-CECNSM '16

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)7
  • Downloads (Last 6 weeks)0
Reflects downloads up to 30 Jan 2025

Other Metrics

Citations

Cited By

View all

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media