research-article

SER Analysis of Multiple Transient Faults in Combinational Logic

Authors:

Georgios Ioannis Paliaroutis,

Pelopidas Tsoumanis,

George Dimitriou,

Georgios I. StamoulisAuthors Info & Claims

SEEDA-CECNSM '16: Proceedings of the SouthEast European Design Automation, Computer Engineering, Computer Networks and Social Media Conference

Pages 36 - 41

https://doi.org/10.1145/2984393.2984414

Published: 25 September 2016 Publication History

Abstract

In the VLSI field, reliability of chips is a major issue and it becomes more significant considering the continuous technology down-scaling. Modern chips are extremely sensitive to various factors such as radiation and, thus, it is crucial to implement tools for the evaluation of their vulnerability to the aforementioned hazards. We present a Soft Error Rate estimation methodology for sequential circuits, based on Monte-Carlo simulations and taking into account Multiple Event Transients. Our tool incorporates the masking effects in order to quantify the number of transients that will be latched from the sequential elements. The verification with HSPICE shows a deviation of about 10%.

References

[1]

Cha, H.; Rudnick, E.M.; Patel, J.H.; Iyer, R.K.; Choi, G.S., "A gate-level simulation environment for alpha-particle- induced transient faults," Computers, IEEE Transactions on, vol.45, no.11, pp.1248, 1256, Nov 1996.

Digital Library

[2]

Dhillon, Y.S.; Diril, A.U.; Chatterjee, A., "Soft-error tolerance analysis and optimization of nanometer circuits," Design, Automation and Test in Europe, 2005. Proceedings, vol., no., pp.288,293 Vol. 1, 7-11 March 2005.

Digital Library

[3]

Zhao, C.; Bai, X.; Dey, S., "A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits," Design Automation Conference, 2004. Proceedings. 41st, vol., no., pp.894,899, 7-11 July 2004.

Digital Library

[4]

Murley, P.C.; Srinivasan, G.R., "Soft-error Monte Carlo modeling program, SEMM," IBM Journal of Research and Development, vol.40, no.1, pp.109,118, Jan. 1996.

Digital Library

[5]

Zhang, M.; Shanbhag, N.R., "A soft error rate analysis (SERA) methodology," Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, vol., no., pp.111,118, 7-11 Nov. 2004.

Digital Library

[6]

Bountas, D.; Stamoulis, G.I., "CARROT -- A Tool for Fast and Accurate Soft Error Rate Estimation", Embedded Computer Systems: Architectures, Modeling, and Simulation Lecture Notes in Computer Science, vol. 4017, pp 331--338, 2006.

Digital Library

[7]

Rao, R.R.; Chopra, K.; Blaauw, D.T.; Sylvester, D.M., "Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.26, no.3, pp.468,479, March 2007.

Digital Library

[8]

AlQuraishi, E.; Al-Roomi, M.; Almukhaizim, S., "Analysis of the soft error susceptibility and failure rate in logic circuits." IEEE Int. Arab J. Inf. Technol. 8.4 (2011): 388--396.

[9]

Miskov-Zivanov, N.; Marculescu, D., "Soft Error Rate Analysis for Sequential Circuits," Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07, vol., no., pp.1,6, 16-20 April 2007.

Digital Library

[10]

Miskov-Zivanov, N.; Marculescu, D., "MARS-C: modeling and reduction of soft errors in combinational circuits," Design Automation Conference, 2006 43rd ACM/IEEE, vol., no., pp.767,772.

Digital Library

[11]

Gill, B.S.; Papachristou, C.; Wolff, F.G., "Soft Delay Error Analysis in Logic Circuits," Design, Automation and Test in Europe, 2006. DATE '06. Proceedings, vol.1, no., pp.1,6, 6-10 March 2006.

Digital Library

[12]

Kiddie, B.T.; Robinson, W.H.; Limbrick, D.B., "Single-Event Multiple-Transients (SEMT): Circuit Characterization and Analysis." IEEE Workshop Silicon Errors in Logic---System Effects (SELSE), Palo Alto, CA, USA. 2013.

[13]

Ebrahimi, M.; Asadi, H.; Tahoori, M.B., "A layout-based approach for Multiple Event Transient analysis," Design Automation Conference (DAC), 2013 50th ACM / EDAC / IEEE, vol., no., pp.1,6, May 29 2013-June 7 2013.

Digital Library

[14]

Miskov-Zivanov, N.; Marculescu, D., "A systematic approach to modeling and analysis of transient faults in logic circuits," Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design, vol., no., pp.408,413, 16-18 March 2009.

Digital Library

[15]

Nanditha, P.R.; Shahbaz, S.; Madhav, P.D., "On the likelihood of multiple bit upsets in logic circuits." arXiv preprint arXiv:1401.1003, 2014.

[16]

Miskov-Zivanov, N.; Marculescu, D., "Multiple Transient Faults in Combinational and Sequential Circuits: A Systematic Approach," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.29, no.10, pp.1614,1627, Oct. 2010.

Digital Library

[17]

Fazeli, M.; Ahmadian, S.N.; Miremadi, S.G.; Asadi, H.; Tahoori, M.B., "Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs)," in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011, vol., no., pp. 1--6, 14-18 March 2011.

[18]

Seifert, N.; Slankard, P.; Kirsch, M.; Narasimham, B.; Zia, V.; Brookreson, C.; Vo, A.; Mitra, S.; Gill, B.; Maiz, J., "Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices," Reliability Physics Symposium Proceedings, 2006. 44th Annual., IEEE International, vol., no., pp.217,225, 26-30 March 2006.

[19]

Messenger, G.C., "Collection of Charge on Junction Nodes from Ion Tracks," Nuclear Science, IEEE Transactions on, vol.29, no.6, pp.2024,2031, Dec. 1982.

[20]

NanGate 45nm Open Cell Library

Cited By

Rohanipoor MGhavami BRaji M(2020)Improving Combinational Circuit Reliability Against Multiple Event Transients via a Partition and Restructuring ApproachIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.290792239:5(1059-1072)Online publication date: May-2020
https://doi.org/10.1109/TCAD.2019.2907922
Paliaroutis GTsoumanis PEvmorfopoulos NDimitriou GStamoulis G(2017)Placement-based SER estimation in the presence of multiple faults in combinational logic2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)10.1109/PATMOS.2017.8106949(1-6)Online publication date: Sep-2017
https://doi.org/10.1109/PATMOS.2017.8106949

Recommendations

Multiple transient faults in combinational and sequential circuits: a systematic approach
Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009

Transient faults in logic circuits are becoming an important reliability concern for future technology nodes. Radiation-induced faults have received significant attention in recent years, while multiple transients originating from a single radiation hit ...
Analysis of Glitch Reconvergence in Combinational Logic SER Estimation
AMS '08: Proceedings of the 2008 Second Asia International Conference on Modelling & Simulation (AMS)

Much effort has been made to estimate SER (Soft error rate) in combinational logic. However, little of them involve glitch reconvergence. In this paper, we discuss how to estimate SER in combinational logic when considering reconvergence. We present ...
Combinational logic SER estimation with the presence of re-convergence
ISQED '09: Proceedings of the 2009 10th International Symposium on Quality of Electronic Design

As transistor feature size scales down, re-convergence takes more and more significant effect to SER (Soft error rate) estimation in combinational logic. In this paper, we propose 4 forms of re-convergence in 2-input logic gates, ROR, RSUB, RAND and ...

Comments

Information & Contributors

Information

Published In

cover image ACM Other conferences

SEEDA-CECNSM '16: Proceedings of the SouthEast European Design Automation, Computer Engineering, Computer Networks and Social Media Conference

September 2016

126 pages

ISBN:9781450348102

DOI:10.1145/2984393

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 25 September 2016

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed limited

Conference

SEEDA-CECNSM '16

SEEDA-CECNSM '16: SouthEast European Design Automation, Computer Engineering, Computer Networks and Social Media Conference

September 25 - 27, 2016

Kastoria, Greece

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

2
Total Citations
View Citations
85
Total Downloads

Downloads (Last 12 months)2
Downloads (Last 6 weeks)0

Reflects downloads up to 05 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Rohanipoor MGhavami BRaji M(2020)Improving Combinational Circuit Reliability Against Multiple Event Transients via a Partition and Restructuring ApproachIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.290792239:5(1059-1072)Online publication date: May-2020
https://doi.org/10.1109/TCAD.2019.2907922
Paliaroutis GTsoumanis PEvmorfopoulos NDimitriou GStamoulis G(2017)Placement-based SER estimation in the presence of multiple faults in combinational logic2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)10.1109/PATMOS.2017.8106949(1-6)Online publication date: Sep-2017
https://doi.org/10.1109/PATMOS.2017.8106949

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten