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Extending Gem5-Garnet for Efficient and Accurate Trace-driven NoC Simulation
Cycle-accurate full-system simulators, such as Gem5, are indispensable for advanced architecture designs. However, as the complexity of the system architectures rises, exploiting the design space with such simulators is becoming very time-consuming. A ...
Improved Flow Control for Minimal Fully Adaptive Routing in 2D Mesh NoC
Routing algorithm has a significant impact on the overall performance of network-on-chip (NoC) based system due to the unbalanced nature of NoC traffic. In this paper, we propose an improved flow control for implementing fully adaptive routing algorithm ...
Reconfigurable Links for Self-Timed On-Chip Communication
Data movement along long interconnects in on-chip networks often consume multiple cycles. Such channels incorporate mechanisms for data storage in order to facilitate pipelining. These links can be effectively abstracted as distributed first-in first-...
A MAC protocol for Reliable Broadcast Communications in Wireless Network-on-Chip
The Wireless Network-on-Chip (WNoC) paradigm holds considerable promise for the implementation of fast and efficient on-chip networks in manycore chips. Among other advantages, wireless communications provide natural broadcast support, a highly ...
On Improving the Performance of Hybrid Wired-Wireless Network-on-Chip Architectures
Recently, hybrid wired-wireless Network-on-Chip (WiNoC) have been proposed to meet the performance and scalability demands of modern System-on-Chip (SoC) design. However, due to the presence of wirelines with multi-hop nodes in the hybrid architecture, ...
Thermal-Aware Adaptive Fault-Tolerant Routing for Hybrid Photonic-Electronic NoC
Microring resonators, key components in on-chip photonic networks, are extremely sensitive to thermal variations, resulting in high failure rate optical transmission. Recently, hybrid photonic-electronic networks-on-chip (HPENoCs) have become popular ...
UCA: An Energy-efficient Hybrid Uncore Architecture in 3D Chip-Multiprocessors to minimize crosstalk
With technology scaling, the number of uncore components increases on a chip in Chip-Multiprocessors (CMPs). As the number of cores increases, power consumption becomes the main concern in Network on Chip (NoC) and Last Level Cache (LLC). Emerging ...
Reliability-Aware Task Scheduling using Clustered Replication for Multi-core Real-Time systems
This paper proposes a model for a new reliability-aware task scheduling method for hard real-time multi-core systems. The proposed method is based on a novel clustered replication which maintains the desired reliability threshold, minimizing both inter-...
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Acceptance Rates
Year | Submitted | Accepted | Rate |
---|---|---|---|
NoCArc '23 | 14 | 5 | 36% |
NoCArc '21 | 9 | 5 | 56% |
NoCArc '19 | 16 | 7 | 44% |
NoCArc '17 | 20 | 6 | 30% |
NoCArc '16 | 20 | 8 | 40% |
NoCArc '15 | 21 | 6 | 29% |
NoCArc '14 | 22 | 9 | 41% |
Overall | 122 | 46 | 38% |