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UCA: An Energy-efficient Hybrid Uncore Architecture in 3D Chip-Multiprocessors to minimize crosstalk

Published: 15 October 2016 Publication History

Abstract

With technology scaling, the number of uncore components increases on a chip in Chip-Multiprocessors (CMPs). As the number of cores increases, power consumption becomes the main concern in Network on Chip (NoC) and Last Level Cache (LLC). Emerging technologies, such as three-dimensional integrated circuits (3D ICs) and non-volatile memories (NVMs) are among the newest solutions to the design of dark-silicon-aware multi/many-core systems. In on-chip interconnection networks, components must be activated for each access, consequently the energy of NoC increases. Although NVMs have many advantages like low leakage and high density, they suffer from shortcomings such as the limited number of write operations and long write operation latency and high energy. In this paper, we propose a new architecture called Uncore-Coding Architecture (UCA) to simultaneously target the short lifetime of NVM LLC and the crosstalk problem of Through-Silicon-Vias (TSVs). This architecture identifies frequent values at runtime in order to encode these values using limited weight codes and therefore reduce the number of bit flips to minimize energy and crosstalk in NoC. Furthermore, this encoding can also improve the life of NVMs integrated into the LLC. Experimental results show that the proposed method improves energy by about 30% on average under PARSEC workloads execution. Moreover, this technique provides Average Memory Access Time approximately, on average, equal to the conventional methods with SRAM cache technology under PARSEC workloads execution.

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Cited By

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  • (2018)NIZCache: Energy-efficient Non-uniform Cache Architecture for Chip-multiprocessors Based on Invalid and Zero Lines2018 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2018.8351128(1-5)Online publication date: 2018
  • (2018)An Energy-Efficient Cache Architecture for Chip-Multiprocessors Based on Non-Uniformity Accesses2018 IEEE Canadian Conference on Electrical & Computer Engineering (CCECE)10.1109/CCECE.2018.8447736(1-4)Online publication date: May-2018
  • (2017)Exploiting non-uniformity of write accesses for designing a high-endurance hybrid Last Level Cache in 3D CMPs2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE)10.1109/CCECE.2017.7946727(1-5)Online publication date: Apr-2017

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cover image ACM Other conferences
NoCArc '16: Proceedings of the 9th International Workshop on Network on Chip Architectures
October 2016
56 pages
ISBN:9781450347921
DOI:10.1145/2994133
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 15 October 2016

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Author Tags

  1. 3D integrated circuit
  2. Chip-Multiprocessors (CMPs)
  3. Crosstalk
  4. Dark-silicon
  5. Last-level Cache (LLC)
  6. Network-on-Chip (NoC)
  7. Non-Volatile Memory (NVM)

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  • Research-article
  • Research
  • Refereed limited

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NoCArc'16

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NoCArc '16 Paper Acceptance Rate 8 of 20 submissions, 40%;
Overall Acceptance Rate 46 of 122 submissions, 38%

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Cited By

View all
  • (2018)NIZCache: Energy-efficient Non-uniform Cache Architecture for Chip-multiprocessors Based on Invalid and Zero Lines2018 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2018.8351128(1-5)Online publication date: 2018
  • (2018)An Energy-Efficient Cache Architecture for Chip-Multiprocessors Based on Non-Uniformity Accesses2018 IEEE Canadian Conference on Electrical & Computer Engineering (CCECE)10.1109/CCECE.2018.8447736(1-4)Online publication date: May-2018
  • (2017)Exploiting non-uniformity of write accesses for designing a high-endurance hybrid Last Level Cache in 3D CMPs2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE)10.1109/CCECE.2017.7946727(1-5)Online publication date: Apr-2017

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