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Reconfigurable Links for Self-Timed On-Chip Communication

Published: 15 October 2016 Publication History

Abstract

Data movement along long interconnects in on-chip networks often consume multiple cycles. Such channels incorporate mechanisms for data storage in order to facilitate pipelining. These links can be effectively abstracted as distributed first-in first-out (FIFO) elements. Using the localized timing and flow control made possible by self-timed communication, this work explores link 'FIFO' designs beyond that of a strictly linear pipeline. In this paper, we present an online technique to detect link bandwidth. We also outline a method to dynamically reconfigure traditional assertive and speculative handshaking techniques for the asynchronous data links. This allows us to tailor network-on-chip (NoC) links according to bandwidth demands. Power and performance characteristics of these data links become a function of the structure and occupancy of the FIFOs. Adjusting link capacity to expected traffic demands allows us to obtain up to 55% dynamic power savings in some cases.

References

[1]
G. Chen et al., "A 340 mv-to-0.9 v 20.2 tb/s source-synchronous hybrid packet/circuit-switched 16 x 16 network-on-chip in 22 nm tri-gate cmos," IEEE Journal of Solid-State Circuits, vol. 50, no. 1, Jan 2015.
[2]
B. Daya et al., "Scorpio: A 36-core research chip demonstrating snoopy coherence on a scalable mesh noc with in-network ordering," in 2014 ACM/IEEE 41st International Symposium on Computer Architecture, June 2014.
[3]
L. Shang et al., "Dynamic voltage scaling with links for power optimization of interconnection networks," in The Ninth International Symposium on High-Performance Computer Architecture, Feb 2003.
[4]
S. Borkar, "Exascale computing -- a fact or a fiction?" in Proceedings of the 2013 IEEE 27th International Symposium on Parallel and Distributed Processing, ser. IPDPS '13, 2013.
[5]
B. Keller et al., "A pausible bisynchronous fifo for gals systems," in Asynchronous Circuits and Systems (ASYNC), 2015 21st IEEE International Symposium on, 2015.
[6]
W. Jiang et al., "A lightweight early arbitration method for low-latency asynchronous 2d-mesh noc's," in Design Automation Conference (DAC), 2015 52nd ACM/EDAC/IEEE, June 2015.
[7]
M. N. Horak et al., "A low-overhead asynchronous interconnection network for gals chip multiprocessors," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 4, April 2011.
[8]
G. Faldamis et al., "A low-latency asynchronous interconnection network with early arbitration resolution," in Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific, Jan 2014.
[9]
E. Kasapaki et al., "Argo: A time-elastic time-division-multiplexed noc using asynchronous routers," in 2014 20th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2014.
[10]
A. K. Kodi et al., "Adaptive channel buffers in on-chip interconnection networks a power and performance analysis," IEEE Transactions on Computers, vol. 57, no. 9, Sept 2008.
[11]
G. Michelogiannakis et al., "Variable-width datapath for on-chip network static power reduction," in 2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), Sept 2014.
[12]
S. E. Lee et al., "A variable frequency link for a power-aware network-on-chip (noc)," Integr. VLSI J., vol. 42, no. 4, Sep. 2009.
[13]
S. Das et al., "Sas: Source asynchronous signaling protocol for asynchronous handshake communication free from wire delay overhead," in IEEE Asynchronous Circuits and Systems Symposium (ASYNC), May 2013.
[14]
H. Han et al., Clocked and asynchronous FIFO characterization and comparison, 2011.

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  • (2017)Design and Analysis of an APU for Exascale Computing2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2017.42(85-96)Online publication date: Feb-2017

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cover image ACM Other conferences
NoCArc '16: Proceedings of the 9th International Workshop on Network on Chip Architectures
October 2016
56 pages
ISBN:9781450347921
DOI:10.1145/2994133
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 15 October 2016

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NoCArc '16 Paper Acceptance Rate 8 of 20 submissions, 40%;
Overall Acceptance Rate 46 of 122 submissions, 38%

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  • (2017)Design and Analysis of an APU for Exascale Computing2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2017.42(85-96)Online publication date: Feb-2017

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