Philip H. W. Leong
Hideharu Amano
João M. P. Cardoso
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Abstract
A summary of contributions made by significant papers from the first 25 years of the Field-Programmable Logic and Applications conference (FPL) is presented. The 27 papers chosen represent those which have most strongly influenced theory and practice in the field.
- M. S. Abdelfattah and V. Betz. 2013. The power of communication: Energy-efficient NoCs for FPGAs. In 2013 23rd International Conference on Field Programmable Logic and Applications (FPL’13). IEEE, 1--8.Google Scholar
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- Altera. 2007. Stratix III Programmable Power. Technical Report WP-01006-1.1. San Jose, CA. https://www.altera.com/en_US/pdfs/literature/wp/wp-01006.pdf.Google Scholar
- Altera. 2010. Increasing Design Functionality with Partial and Dynamic Reconfiguration in 28-nm FPGAs. Technical Report WP-01137-1.0. https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/ literature/wp/wp-01137-stxv-dynamic-partial-reconfig.pdf.Google Scholar
- J. H. Anderson and F. N. Najm. 2006. Active leakage power optimization for FPGAs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25, 3 (March 2006), 423--437. Google ScholarDigital Library
- S. Asano, T. Maruyama, and Y. Yamaguchi. 2009. Performance comparison of FPGA, GPU and CPU in image processing. In International Conference on Field Programmable Logic and Applications, 2009 (FPL’09). IEEE, 126--131.Google ScholarCross Ref
- J. Auerbach, D. F. Bacon, P. Cheng, and R. Rabbah. 2010. Lime: A Java-compatible and synthesizable language for heterogeneous architectures. In Proceedings of the ACM International Conference on Object Oriented Programming Systems Languages and Applications (OOPSLA’10). ACM, New York, NY, 89--108. Google ScholarDigital Library
- B. Baldwin, A. Byrne, L. Lu, M. Hamilton, N. Hanley, M. ONeill, and W. P. Marnane. 2010. FPGA implementations of the round two SHA-3 candidates. In 2010 International Conference on Field Programmable Logic and Applications (FPL’10). IEEE, 400--407. Google ScholarDigital Library
- V. Baumgarte, G. Ehlers, F. May, A. Nückel, M. Vorbach, and M. Weinhardt. 2003. PACT XPPA self-reconfigurable data processing architecture. Journal of Supercomputing 26, 2 (2003), 167--184. Google ScholarDigital Library
- C. Beckhoff, D. Koch, and J. Torresen. 2012. Go ahead: A partial reconfiguration framework. In Proceedings of the 20th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM’12). 37--44. Google ScholarDigital Library
- V. Betz and J. Rose. 1997. VPR: A new packing, placement and routing tool for FPGA research. In Field-Programmable Logic and Applications, W. Luk, P. Y. K. Cheung, and M. Glesner (Eds.). Lecture Notes in Computer Science, Vol. 1304. Springer, Berlin, 213--222. Google ScholarDigital Library
- A. Bitar, M. Abdelfattah, and V. Betz. 2015. Bringing programmability to the data plane: Packet processing with a NoC-enhanced FPGA. In 2015 International Conference on Field-Programmable Technology (FPT’15).Google Scholar
- A. Bitar, J. Cassidy, N. E. Jerger, and V. Betz. 2014. Efficient and programmable ethernet switching with a NoC-enhanced FPGA. In Proceedings of the 10th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS’14). ACM, New York, NY, 89--100. Google ScholarDigital Library
- C. Bobda, A. Ahmadinia, M. Majer, J. Teich, S. Fekete, and J. Veen. 2005. Dynoc: A dynamic infrastructure for communication in dynamically reconfugurable devices. In Proceedings of the International Field Programmable Logic and Applications Conference. 153--158.Google Scholar
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- B.C. Brodie, R. K. Cytron, and D. E. Taylor. 2006. A scalable architecture for high-throughput regular-expression pattern matching. In 33rd International Symposium on Computer Architecture, 2006 (ISCA’06). 191--202. Google ScholarDigital Library
- M. Butts, A. M. Jones, and P. Wasson. 2007. A structural object programming model, architecture, chip and tools for reconfigurable computing. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines. 55--64. Google ScholarDigital Library
- E. Caspi, M. Chu, R. Huang, J. Yeh, J. Wawrzynek, and A. DeHon. 2000. Stream computations organized for reconfigurable execution (SCORE). In Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing, Reiner Hartenstein and Herbert Grünbacher (Eds.). Lecture Notes in Computer Science, Vol. 1896. Springer, Berlin, 605--614. Google ScholarDigital Library
- C. R. Clark and D. E. Schimmel. 2004a. Scalable pattern matching for high speed networks. In 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2004 (FCCM’04). 249--257. Google ScholarDigital Library
- C. R. Clark and D. E. Schimmel. 2004b. Scalable pattern matching for high speed networks. In Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’04). IEEE Computer Society, 249--257. http://dl.acm.org/citation.cfm?id=1025123.1025834. Google ScholarDigital Library
- A. DeHon, Y. Markovsky, E. Caspi, M. Chu, R. Huang, S. Perissakis, L. Pozzi, J. Yeh, and J. Wawrzynek. 2006. Stream computations organized for reconfigurable execution. Journal of Microprocessors and Microsystems 30, 6 (September 2006), 334--354.Google ScholarCross Ref
- P. D. Düben and T. N. Palmer. 2014. Benchmark tests for numerical weather forecasts on inexact hardware. Monthly Weather Review 142, 10 (2014), 3809--3829.Google ScholarCross Ref
- C. Ebeling, D. C. Cronquist, and P. Franklin. 1996. RaPiD reconfigurable pipelined datapath. In Field-Programmable Logic Smart Applications, New Paradigms and Compilers, Reiner Hartenstein and Manfred Glesner (Eds.). Lecture Notes in Computer Science, Vol. 1142. Springer, Berlin, 126--135. Google ScholarDigital Library
- R. Enzler, C. Plessl, and M. Platzner. 2003. Virtualizing hardware with multi-context reconfigurable arrays. In Field Programmable Logic and Applications, Peter Y. K. Cheung and George A. Constantinides (Eds.). Lecture Notes in Computer Science, Vol. 2778. Springer, Berlin, 151--160.Google Scholar
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- L. Gan, H. Fu, W. Luk, C. Yang, W. Xue, X. Huang, Y. Zhang, and G. Yang. 2013. Accelerating solvers for global atmospheric equations through mixed-precision data flow engine. In 2013 23rd International Conference on Field Programmable Logic and Applications (FPL’13). IEEE, 1--6.Google Scholar
- A. Gayasen, K. Lee, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, and T. Tuan. 2004. A dual-VDD low power FPGA architecture. In Field Programmable Logic and Applications, Jürgen Becker, Marco Platzner, and Serge Vernalde (Eds.). Lecture Notes in Computer Science, Vol. 3203. Springer, Berlin, 145--157.Google Scholar
- R. Glein, B. Schmidt, F. Rittner, J. Teich, and D. Ziener. 2014. A self-adaptive SEU mitigation system for FPGAs with an internal block RAM radiation particle sensor. In 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM’14). 251--258. Google ScholarDigital Library
- M. Gokhale, D. Dubois, A. Dubois, M. Boorman, S. Poole, and V. Hogsett. 2002. Granidt: Towards gigabit rate network intrusion detection technology. In Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream, Manfred Glesner, Peter Zipf, and Michel Renovell (Eds.). Lecture Notes in Computer Science, Vol. 2438. Springer, Berlin, 404--413. Google ScholarDigital Library
- M. B. Gokhale and P. S. Graham. 2006. Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays. Springer Science 8 Business Media. Google ScholarDigital Library
- J. Guajardo, S. S. Kumar, G.-J. Schrijen, and P. Tuyls. 2007. Physical unclonable functions and public-key crypto for FPGA IP protection. In International Conference on Field Programmable Logic and Applications, 2007 (FPL’07). IEEE, 189--195.Google ScholarCross Ref
- S. D. Haynes, P. Y. K. Cheung, W. Luk, and J. Stone. 1999. SONIC -- A plug-in architecture for video processing. In Field Programmable Logic and Applications, Patrick Lysaght, James Irvine, and Reiner Hartenstein (Eds.). Lecture Notes in Computer Science, Vol. 1673. Springer, Berlin, 21--30. Google ScholarDigital Library
- S. D. Haynes, H. G. Epsom, R. J. Cooper, and P. L. McAlpine. 2002. UltraSONIC: A reconfigurable architecture for video image processing. In Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. Springer, 482--491. Google ScholarDigital Library
- J. Heiner, B. Sellers, M. Wirthlin, and J. Kalb. 2009. FPGA partial reconfiguration via configuration scrubbing. In International Conference on Field Programmable Logic and Applications, 2009 (FPL’09). IEEE, 99--104.Google ScholarCross Ref
- M. Hutton. 2015. Architectural paths to faster and more robust FPGAs (keynote). In 2015 International Conference on Field-Programmable Technology (FPT’15).Google Scholar
- H. Kalte and M. Porrmann. 2005. Context saving and restoring for multitasking in reconfigurable systems. In International Conference on Field Programmable Logic and Applications, 2005. IEEE, 223--228.Google ScholarCross Ref
- N. Kapre and A. DeHon. 2011. VLIW-SCORE: Beyond C for sequential control of SPICE FPGA acceleration. In 2011 International Conference on Field-Programmable Technology (FPT’11). 1--9.Google Scholar
- C. Kim, M. Chung, Y. Cho, M. Konijnenburg, S. Ryu, and J. Kim. 2012. ULP-SRP: Ultra low power samsung reconfigurable processor for biomedical applications. In 2012 International Conference on Field-Programmable Technology (FPT’12). 329--334.Google Scholar
- D. Koch, C. Beckhoff, and J. Teich. 2008. ReCoBus-Builder: A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAs. In International Conference on Field Programmable Logic and Applications, 2008 (FPL’08). IEEE, 119--124.Google Scholar
- C. Kohn. 2015. Partial Reconfiguration of a Hardware Accelerator with Vivado Design Suite. Technical Report XAPP1231. San Jose, CA. http://www.xilinx.com/support/documentation/application_notes/xapp1231-pa rtial-reconfig-hw-accelerator-vivado.pdf.Google Scholar
- S. Kumar, S. Dharmapurikar, F. Yu, P. Crowley, and J. Turner. 2006. Algorithms to accelerate multiple regular expressions matching for deep packet inspection. In Proceedings of the 2006 Conference on Applications, Technologies, Architectures, and Protocols for Computer Communications (SIGCOMM’06). ACM, New York, NY, 339--350. Google ScholarDigital Library
- P. H. W. Leong, H. Amano, J. Anderson, K. Bertels, J. M. P. Cardoso, O. Diessel, G. Gogniat, M. Hutton, JunKyu Lee, W. Luk, P. Lysaght, M. Platzner, V. K. Prasanna, T. Rissa, C. Silvano, H. So, and Yu Wang. 2015. Significant papers from the first 25 years of the FPL conference. In Proc. International Conference on Field Programmable Logic and Applications (FPL). 1--3.Google ScholarCross Ref
- D. Lewis, D. Cashman, M. Chan, J. Chromczak, G. Lai, A. Lee, T. Vanderhoek, and H. Yu. 2013. Architectural enhancements in stratix V™. In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA’13). ACM, New York, NY, 147--156. Google ScholarDigital Library
- F. Li, Y. Lin, L. He, D. Chen, and J. Cong. 2005. Power modeling and characteristics of field programmable gate arrays. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24, 11 (2005), 1712--1724. Google ScholarDigital Library
- O. Lindtjorn, R. Clapp, O. Pell, Haohuan Fu, M. Flynn, and Haohuan Fu. 2011. Beyond traditional microprocessors for geoscience high-performance computing applications. IEEE Micro 31, 2 (March 2011), 41--49. Google ScholarDigital Library
- E. Lübbers and M. Platzner. 2009. ReconOS: Multithreaded programming for reconfigurable computers. ACM Transactions on Embedded Computing Systems (TECS) 9, 1 (2009), 8. Google ScholarDigital Library
- A. Ludwin and V. Betz. 2011. Efficient and deterministic parallel placement for FPGAs. ACM Transactions on Design Automation of Electronic Systems 16, 3, Article 22 (June 2011), 23 pages. Google ScholarDigital Library
- J. Luu, J. Goeders, M. Wainberg, A. Somerville, T. Yu, K. Nasartschuk, M. Nasr, S. Wang, T. Liu, N. Ahmed, K. B. Kent, J. Anderson, J. Rose, and V. Betz. 2014. VTR 7.0: Next generation architecture and CAD system for FPGAs. ACM Transactions on Reconfigurable Technology and Systems 7, 2, Article 6 (July 2014), 30 pages. Google ScholarDigital Library
- P. Lysaght, B. Blodget, J. Mason, J. Young, and B. Bridgford. 2006. Invited paper: Enhanced architectures, design methodologies and CAD tools for dynamic reconfiguration of Xilinx FPGAs. In International Conference on Field Programmable Logic and Applications, 2006 (FPL’06). IEEE, 1--6.Google ScholarCross Ref
- P. Lysaght and J. Dunlop. 1994. Dynamic reconfiguration of FPGAs. In Selected Papers from the Oxford 1993 International Workshop on Field Programmable Logic and Applications on More FPGAs. Abingdon EE8CS Books, Oxford, UK, 82--94. Google ScholarDigital Library
- R. Maes and I. Verbauwhede. 2010. Physically unclonable functions: A study on the state of the art and future research directions. In Towards Hardware-Intrinsic Security. Springer, 3--37.Google Scholar
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- B. Mei, S. Vernalde, D. Verkest, H. De Man, and R. Lauwereins. 2003. ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix. In Field Programmable Logic and Applications, Peter Y. K. Cheung and George A. Constantinides (Eds.). Lecture Notes in Computer Science, Vol. 2778. Springer, Berlin, 61--70.Google Scholar
- O. Mencer, H. Hübert, M. Morf, and M. J. Flynn. 2000. StReAm: Object-oriented programming of stream architectures using PAM-Blox. In Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing, Reiner Hartenstein and Herbert Grünbacher (Eds.). Lecture Notes in Computer Science, Vol. 1896. Springer, Berlin, 595--604. Google ScholarDigital Library
- U. Meyer-Baese and U. Meyer-Baese. 2007. Digital Signal Processing with Field Programmable Gate Arrays. Vol. 65. Springer. Google ScholarDigital Library
- F. Moraes, N. Calazans, A. Mello, L. Möller, and L. Ost. 2004. HERMES: An infrastructure for low area overhead packet-switching networks on chip. Integrated VLSI Journal 38, 1 (October 2004), 69--93. Google ScholarDigital Library
- NIST. 2015. SHA-3 Standard: Permutation-Based Hash and Extendable-Output Functions. Federal Information Processing Standards Publication FIPS Pub 202. http://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.202.pdf.Google Scholar
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- T. F. Oliver, B. Schmidt, and D. L. Maskell. 2005. Reconfigurable architectures for bio-sequence database scanning on FPGAs. IEEE Transactions on Circuits and Systems II: Express Briefs, 52, 12 (2005), 851--855.Google ScholarCross Ref
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- R. J. Petersen and B. L. Hutchings. 1995. An assessment of the suitability of FPGA-based systems for use in digital signal processing. In Field-Programmable Logic and Applications, Will Moore and Wayne Luk (Eds.). Lecture Notes in Computer Science, Vol. 975. Springer, Berlin, 293--302. Google ScholarDigital Library
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- The First 25 Years of the FPL Conference: Significant Papers
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