skip to main content
research-article

Power-Utility-Driven Write Management for MLC PCM

Published: 20 April 2017 Publication History

Abstract

Phase change memory (PCM) is a promising alternative to Dynamic Random Access Memory (DRAM) as main memory due to its merits of high density and low leakage power. Multi-level Cell (MLC) PCM is more attractive than Single-level Cell (SLC) PCM, because it can store multiple bits per cell to achieve higher density and lower per-bit cost. With the iterative program-verify write technique, MLC PCM writes demand at much higher power than DRAM writes, while the power supply system of MLC memory system is similar to that of DRAM, and the power capability is limited. The incompatibility of high write power and limited power budget results in the degradation of the write throughput and performance in MLC PCM. In this work, we investigate both write scheduling policy and power management to improve the MLC power utility and alleviate the negative impacts induced by high write power. We identify the power-utility-driven write scheduling as an online bin-packing problem and then derive a power-utility-driven scheduling (PUDS) policy from the First Fit algorithm to improve the write power usage. Based on the ramp-down characteristic of the SET pulse (the pulse changes the PCM to high resistance), we propose the SET Power Amortization (SPA) policy, which proactively reclaims the power tokens at the intra-SET level to promote the power utilization. Our experimental results demonstrate that the PUDS and SPA respectively achieve 24% and 27% performance improvement over the state-of-the-art power management technique, and the PUDS8SPA has an overall 31% improvement of the power utility and 50% increase of performance compared to the baseline system.

References

[1]
Ferdinando Bedeschi, Rich Fackenthal, Claudio Resta, Enzo Michele Donzè, Meenatchi Jagasivamani, Egidio Cassiodoro Buda, Fabio Pellizzer, David W. Chow, Alessandro Cabrini, Giacomo Matteo Angelo Calvi, and others. 2009. A bipolar-selected phase change memory featuring multi-level cell storage. IEEE J. Solid-State Circ. 44, 1 (2009), 217--227.
[2]
Geoffrey W. Burr, Alvaro Padilla, Michele Franceschini, Bryan Jackson, Diego G. Dupouy, Charles T. Rettner, Kailash Gopalakrishnan, Rohit Shenoy, and John Karidis. 2010. The inner workings of phase change memory: Lessons from prototype PCM devices. In Proceedings of the 2010 IEEE GLOBECOM Workshops (GC Wkshps). IEEE, 1890--1894.
[3]
W. C. Chien, Y. H. Ho, H. Y. Cheng, M. BrightSky, C. J. Chen, C. W. Yeh, T. S. Chen, W. Kim, S. Kim, J. Y. Wu, A. Ray, R. Bruce, Y. Zhu, H. Y. Ho, H. L. Lung, and C. Lam. 2015. A novel self-converging write scheme for 2-bits/cell phase change memory for storage class memory (SCM) application. In Proceedings of the 2015 Symposium on VLSI Technology (VLSI Technology). T100--T101.
[4]
Sangyeun Cho and Hyunjin Lee. 2009. Flip-n-write: A simple deterministic technique to improve PRAM write performance, energy and endurance. In Proceedings of the 42nd Annual IEEEACM International Symposium on Microarchitecture (MICRO 42). ACM, New York, NY, 347--357.
[5]
Xiangyu Dong, Cong Xu, Yuan Xie, and N. P. Jouppi. 2012. NVSim: A circuit-level performance, energy, and area model for emerging nonvolatile memory. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 31, 7 (July 2012), 994--1007.
[6]
Andrew Hay, Karin Strauss, Timothy Sherwood, Gabriel H. Loh, and Doug Burger. 2011. Preventing PCM banks from seizing too much power. In Proceedings of the 44th Annual IEEEACM International Symposium on Microarchitecture (MICRO-44). ACM, New York, NY, 186--195.
[7]
John L. Henning. 2006. SPEC CPU2006 benchmark descriptions. ACM SIGARCH Comput. Arch. News 34, 4 (Sept. 2006), 1--17.
[8]
International Technology Roadmap for Semiconductors (ITRS). 2015. Semiconductor Industry Association (2015).
[9]
Bruce Jacob, Spencer Ng, and David Wang. 2010. Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann, San Francisco, CA.
[10]
Lei Jiang, Youtao Zhang, Bruce R. Childers, and Jun Yang. 2012a. FPB: Fine-grained power budgeting to improve write throughput of multi-level cell phase change memory. In Proceedings of the 45th Annual IEEEACM International Symposium on Microarchitecture (MICRO-45). IEEE Computer Society, Washington, DC, 1--12.
[11]
Lei Jiang, Bo Zhao, Youtao Zhang, Jun Yang, and B. R. Childers. 2012b. Improving write operations in MLC phase change memory. In Proceedings of the 2012 IEEE 18th International Symposium on High Performance Computer Architecture (HPCA). IEEE, 1--10.
[12]
Madhura Joshi, Wangyuan Zhang, and Tao Li. 2011. Mercury: A fast and energy-efficient multi-level cell based phase change memory system. In Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA). IEEE, 345--356.
[13]
Athanasios Kiouseloglou, Gabriele Navarro, Véronique Sousa, Alain Persico, Anne Roule, Alessandro Cabrini, Guido Torelli, Sylvian Maitrejean, Gilles Reimbold, Barbara De Salvo, and others. 2014. A novel programming technique to boost low-resistance state performance in ge-rich GST phase change memory. IEEE Trans. Electron Devices 61, 5 (May 2014), 1246--1254.
[14]
Richard E. Korf. 2002. A new algorithm for optimal bin packing. In Eighteenth National Conference on Artificial Intelligence. American Association for Artificial Intelligence, Menlo Park, CA, 731--736.
[15]
Benjamin C. Lee, Engin Ipek, Onur Mutlu, and Doug Burger. 2009. Architecting phase change memory as a scalable dram alternative. In Proceedings of the 36th Annual International Symposium on Computer Architecture (ISCA’09). ACM, New York, NY, 2--13.
[16]
Yebin Lee, Soontae Kim, Seokin Hong, and Jongmin Lee. 2013. Skinflint DRAM system: Minimizing DRAM chip writes for low power. In Proceedings of the 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA). IEEE, 25--34.
[17]
Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yuan Xie, and Tingting Huang. 2013. Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs. VLSI J. Integr. 46, 1 (2013), 1--9.
[18]
Ren-Shuo Liu, De-Yu Shen, Chia-Lin Yang, and others. 2014. NVM duet: Unified working memory and persistent store architecture. In Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’14). ACM, New York, NY, 455--470.
[19]
Gabriel H. Loh and Yuan Xie. 2010. 3D stacked microprocessor: Are we there yet? IEEE Micro 30, 3 (May 2010), 60--64.
[20]
Krishna T. Malladi, Benjamin C. Lee, Frank A. Nothaft, Christos Kozyrakis, Karthika Periyathambi, and Mark Horowitz. 2012. Towards energy-proportional datacenter memory with mobile DRAM. In Proceedings of the 39th Annual International Symposium on Computer Architecture (ISCA’12). IEEE Computer Society, Washington, DC, 37--48.
[21]
Technology Inc. Micron. 2016. DDR4: Advantages of migrating from DDR3. Retrieved from https://www.micron.com/products/dram/ddr3-to-ddr4.
[22]
Onur Mutlu and Thomas Moscibroda. 2007. Stall-time fair memory access scheduling for chip multiprocessors. In Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 40). IEEE Computer Society, Washington, DC, 146--160.
[23]
Onur Mutlu and Thomas Moscibroda. 2008. Parallelism-aware batch scheduling: Enhancing both performance and fairness of shared DRAM systems. In Proceedings of the 35th Annual International Symposium on Computer Architecture (ISCA’08). IEEE Computer Society, Washington, DC, 63--74.
[24]
Ron Neale. 2015. IBM solves PCM problems with projections. Retrieved from http://www.eetimes.com/author.asp?doc_id=1327596.
[25]
T. Nirschl, J. B. Philipp, T. D. Happ, Geoffrey W. Burr, B. Rajendran, M. H. Lee, A. Schrott, M. Yang, M. Breitwisch, C. F. Chen, E. Joseph, M. Lamorey, R. Cheek, S.-H. Chen, S. Zaidi, S. Raoux, Y. C. Chen, Y. Zhu, R. Bergmann, H. L. Lung, and C. Lam. 2007. Write strategies for 2 and 4-bit multi-level phase-change memory. In Proceedings of the 2007 IEEE International Electron Devices Meeting. IEEE, 461--464.
[26]
Alvaro Padilla, Geoffrey W. Burr, Charles T. Rettner, Teya Topuria, Philip M. Rice, Bryan Jackson, Kumar Virwani, Andrew J. Kellock, Diego Dupouy, Anthony Debunne, and others. 2011. Voltage polarity effects in Ge2Sb2Te5-based phase change memory devices. J. Appl. Phys. 110, 5 (2011), 054501.
[27]
Alvaro Padilla, Geoffrey W. Burr, K. Virwani, A. Debunne, C. T. Rettner, T. Topuria, P. M. Rice, B. Jackson, D. Dupouy, A. J. Kellock, R. M. Shelby, K. Gopalakrishnan, R. S. Shenoy, and B. N. Kurdi. 2010. Voltage polarity effects in GST-based phase change memory: Physical origins and implications. In 2010 International Electron Devices Meeting. 29.4.1--29.4.4.
[28]
Nikolaos Papandreou, Aggeliki Pantazi, Abu Sebastian, M. Breitwisch, C. Lam, Haralampos Pozidis, and Evangelos Eleftheriou. 2010. Multilevel phase-change memory. In Proceedings of the 2010 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS). IEEE, 1017--1020.
[29]
Nikolaos Papandreou, Haralampos Pozidis, Aggeliki Pantazi, Abu Sebastian, M. Breitwisch, C. Lam, and Evangelos Eleftheriou. 2011. Programming algorithms for multilevel phase-change memory. In 2011 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 329--332.
[30]
Avadh Patel, Furat Afram, Shunfei Chen, and Kanad Ghose. 2011. MARSS: A full system simulator for multicore x86 CPUs. In Proceedings of the 48th Design Automation Conference (DAC’11). ACM, New York, NY, 1050--1055.
[31]
Haris Pozidis, Nikolaos Papandreou, Aradoaei Sebastian, Thomas Mittelholzer, M. BrightSky, Chris Lam, and Evangelos Eleftheriou. 2013. Reliable MLC data storage and retention in phase-change memory after endurance cycling. In Proceedings of the 2013 5th IEEE International Memory Workshop (IMW). IEEE, 100--103.
[32]
Moinuddin K. Qureshi, Michele M. Franceschini, Ashish Jagmohan, and Luis A. Lastras. 2012. PreSET: Improving performance of phase change memories by exploiting asymmetry in write times. In Proceedings of the 39th Annual International Symposium on Computer Architecture (ISCA’12). IEEE Computer Society, Washington, DC, 380--391.
[33]
Moinuddin K. Qureshi, Michele M. Franceschini, Luis Lastras-Monta, and others. 2010a. Improving read performance of phase change memories via write cancellation and write pausing. In 2010 IEEE 16th International Symposium on High Performance Computer Architecture (HPCA). 1--11.
[34]
Moinuddin K. Qureshi, Michele M. Franceschini, Luis A. Lastras-Montaño, and John P. Karidis. 2010b. Morphable memory system: A robust architecture for exploiting multi-level phase change memories. In Proceedings of the 37th Annual International Symposium on Computer Architecture (ISCA’10). ACM, New York, NY, 153--162.
[35]
Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, and Jude A. Rivers. 2009. Scalable high performance main memory system using phase-change memory technology. In Proceedings of the 36th Annual International Symposium on Computer Architecture (ISCA’09). ACM, New York, NY, 24--33.
[36]
Simone Raoux, Geoffrey W. Burr, Matthew J. Breitwisch, Charles T. Rettner, Yi-Chou Chen, Robert M. Shelby, Martin Salinga, Daniel Krebs, S.-H. Chen, Hsiang-Lan Lung, and others. 2008. Phase-change random access memory: A scalable technology. IBM J. Res. Dev. 52, 4.5 (July 2008), 465--479.
[37]
Paul Rosenfeld, Elliott Cooper-Balis, and Bruce Jacob. 2011. DRAMSim2: A cycle accurate memory system simulator. Comput. Arch. Lett. 10, 1 (Jan. 2011), 16--19.
[38]
Electronics Co. Ltd. Samsung. 2013. Samsung DDR4 SDRAM. Retrieved from http://159.226.251.229/videoplayer/DDR4_Brochure-0.pdf.
[39]
Abu Sebastian, Manuel Le Gallo, and Daniel Krebs. 2014. Crystal growth within a phase change memory cell. Nat. Commun. 5 (2014), 4314.
[40]
Manjunath Shevgoor, Jung-Sik Kim, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, and Aniruddha N. Udipi. 2013. Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device. In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46). ACM, New York, NY, 198--209.
[41]
H. S. Philip Wong, Simone Raoux, SangBum Kim, Jiale Liang, John P. Reifenberg, Bipin Rajendran, Mehdi Asheghi, and Kenneth E. Goodson. 2010. Phase change memory. Proc. IEEE 98, 12 (Dec. 2010), 2201--2227.
[42]
Qi Wu and Tong Zhang. 2011. Design techniques to facilitate processor power delivery in 3-D processor-DRAM integrated systems. IEEE Trans. VLSI Syst. 19, 9 (Sept. 2011), 1655--1666.
[43]
Doe Hyun Yoon, Jichuan Chang, Naveen Muralimanohar, and Parthasarathy Ranganathan. 2012. BOOM: Enabling mobile memory based low-power server DIMMs. In Proceedings of the 39th Annual International Symposium on Computer Architecture (ISCA’12). IEEE Computer Society, Washington, DC, 25--36.
[44]
Ping Zhou, Yu Du, Youtao Zhang, and Jun Yang. 2010. Fine-grained QoS scheduling for PCM-based main memory. In Proceedings of the 2010 IEEE International Symposium on Parallel Distributed Processing (IPDPS). 1--12.
[45]
Ping Zhou, Bo Zhao, Jun Yang, and Youtao Zhang. 2009. A durable and energy efficient main memory using phase change memory technology. In Proceedings of the 36th Annual International Symposium on Computer Architecture (ISCA’09). ACM, New York, NY, 14--23.

Cited By

View all
  • (2020)Joint resource block and power allocation in heterogeneous cellular networks with different backhaul capacity limitationsTransactions on Emerging Telecommunications Technologies10.1002/ett.406431:9Online publication date: 14-Sep-2020
  • (2019)An Efficient Spare-Line Replacement Scheme to Enhance NVM SecurityProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317767(1-6)Online publication date: 2-Jun-2019
  • (2019)An Overview of In-memory Processing with Emerging Non-volatile Memory for Data-intensive ApplicationsProceedings of the 2019 Great Lakes Symposium on VLSI10.1145/3299874.3319452(381-386)Online publication date: 13-May-2019

Index Terms

  1. Power-Utility-Driven Write Management for MLC PCM

      Recommendations

      Comments

      Information & Contributors

      Information

      Published In

      cover image ACM Journal on Emerging Technologies in Computing Systems
      ACM Journal on Emerging Technologies in Computing Systems  Volume 13, Issue 3
      Special Issue on Hardware and Algorithms for Learning On-a-chip and Special Issue on Alternative Computing Systems
      July 2017
      418 pages
      ISSN:1550-4832
      EISSN:1550-4840
      DOI:10.1145/3051701
      • Editor:
      • Yuan Xie
      Issue’s Table of Contents
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Journal Family

      Publication History

      Published: 20 April 2017
      Accepted: 01 September 2016
      Revised: 01 February 2016
      Received: 01 October 2015
      Published in JETC Volume 13, Issue 3

      Permissions

      Request permissions for this article.

      Check for updates

      Author Tags

      1. Phase change memory
      2. main memory
      3. multi-level
      4. optimization
      5. power
      6. write management

      Qualifiers

      • Research-article
      • Research
      • Refereed

      Funding Sources

      • National Basic Research Program of China (973 Program)
      • National Natural Science Foundation of China (NSFC Program)

      Contributors

      Other Metrics

      Bibliometrics & Citations

      Bibliometrics

      Article Metrics

      • Downloads (Last 12 months)5
      • Downloads (Last 6 weeks)2
      Reflects downloads up to 15 Feb 2025

      Other Metrics

      Citations

      Cited By

      View all
      • (2020)Joint resource block and power allocation in heterogeneous cellular networks with different backhaul capacity limitationsTransactions on Emerging Telecommunications Technologies10.1002/ett.406431:9Online publication date: 14-Sep-2020
      • (2019)An Efficient Spare-Line Replacement Scheme to Enhance NVM SecurityProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317767(1-6)Online publication date: 2-Jun-2019
      • (2019)An Overview of In-memory Processing with Emerging Non-volatile Memory for Data-intensive ApplicationsProceedings of the 2019 Great Lakes Symposium on VLSI10.1145/3299874.3319452(381-386)Online publication date: 13-May-2019

      View Options

      Login options

      Full Access

      View options

      PDF

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader

      Figures

      Tables

      Media

      Share

      Share

      Share this Publication link

      Share on social media