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Hardware resource estimation for heterogeneous FPGA-based SoCs

Published: 03 April 2017 Publication History

Abstract

The increasing complexity of recent System-on-Chip (SoC) designs introduces new challenges for design space exploration tools. In addition to the time-to-market challenge, designers need to estimate rapidly and accurately both performance and area occupation of complex and diverse applications. High-Level Synthesis (HLS) has been emerged as an attractive solution for designers to address these challenges in order to explore a large number of SoC configurations. In this paper, we target hybrid CPU-FPGA based SoCs. We propose a high-level area estimation tool based on an analytic model without requiring register-transfer level (RTL) implementations. This technique allows to estimate the required FPGA resources at the source code level to map an application to a hybrid CPU-FPGA system. The proposed model also enables a fast design exploration with different trade-offs through HLS optimization pragmas. Experimental results show that the proposed area analytic model provides an accurate estimation with a negligible error (less than 5+) compared to RTL implementations.

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Cited By

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  • (2023)Scalable QKD Postprocessing System With Reconfigurable Hardware AcceleratorIEEE Transactions on Quantum Engineering10.1109/TQE.2023.33260934(1-14)Online publication date: 2023
  • (2022)Machine Learning Based Framework for Fast Resource Estimation of RTL Designs Targeting FPGAsACM Transactions on Design Automation of Electronic Systems10.1145/355504728:2(1-16)Online publication date: 29-Sep-2022
  • (2022)Mapping-Aware Kernel Partitioning Method for CGRAs Assisted by Deep LearningIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2021.310774633:5(1213-1230)Online publication date: 1-May-2022
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    cover image ACM Conferences
    SAC '17: Proceedings of the Symposium on Applied Computing
    April 2017
    2004 pages
    ISBN:9781450344869
    DOI:10.1145/3019612
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    Published: 03 April 2017

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    Author Tags

    1. FPGA
    2. HLS
    3. SoC
    4. hardware accelerator

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    SAC 2017: Symposium on Applied Computing
    April 3 - 7, 2017
    Marrakech, Morocco

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    Cited By

    View all
    • (2023)Scalable QKD Postprocessing System With Reconfigurable Hardware AcceleratorIEEE Transactions on Quantum Engineering10.1109/TQE.2023.33260934(1-14)Online publication date: 2023
    • (2022)Machine Learning Based Framework for Fast Resource Estimation of RTL Designs Targeting FPGAsACM Transactions on Design Automation of Electronic Systems10.1145/355504728:2(1-16)Online publication date: 29-Sep-2022
    • (2022)Mapping-Aware Kernel Partitioning Method for CGRAs Assisted by Deep LearningIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2021.310774633:5(1213-1230)Online publication date: 1-May-2022
    • (2021)On Predictable Reconfigurable System DesignACM Transactions on Architecture and Code Optimization10.1145/343699518:2(1-28)Online publication date: 9-Feb-2021
    • (2020)Rapid High-Level FPGA Resource Estimation for a Novel Heterogeneous Platform Scheduling Scheme2020 11th International Conference on Information and Communication Systems (ICICS)10.1109/ICICS49469.2020.239515(378-381)Online publication date: Apr-2020
    • (2020)Towards Automatic High-Level Code Deployment on Reconfigurable Platforms: A Survey of High-Level Synthesis Tools and ToolchainsIEEE Access10.1109/ACCESS.2020.30240988(174692-174722)Online publication date: 2020
    • (2019)Automatic Energy-Minimized HW/SW Partitioning for FPGA-Accelerated MPSoCsIEEE Embedded Systems Letters10.1109/LES.2019.290122411:3(93-96)Online publication date: Sep-2019

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