Marco Danelutto
ABSTRACT
High-level parallel programming is a de-facto standard approach to develop parallel software with reduced time to development. High-level abstractions are provided by existing frameworks as pragma-based annotations in the source code, or through pre-built parallel patterns that recur frequently in parallel algorithms, and that can be easily instantiated by the programmer to add a structure to the development of parallel software. In this paper we focus on this second approach and we propose P3ARSEC, a benchmark suite for parallel pattern-based frameworks consisting of a representative subset of PARSEC applications. We analyse the programmability advantages and the potential performance penalty of using such high-level methodology with respect to hand-made parallelisations using low-level mechanisms. The results are obtained on the new Intel Knights Landing multicore, and show a significantly reduced code complexity with comparable performance.
- B. Chapman, G. Jost, and R. v. d. Pas, Using OpenMP: Portable Shared Memory Parallel Programming. The MIT Press, 2007. Google Scholar
Digital Library
- A. Duran, E. Ayguadé, R. M. Badia, J. Labarta, L. Martinell, X. Martorell, and J. Planas, "Ompss: a proposal for programming heterogeneous multi-core architectures," Parallel Processing Letters, vol. 21, pp. 173--193, 2011. Google ScholarCross Ref
- T. Mattson, B. Sanders, and B. Massingill, Patterns for parallel programming. Addison-Wesley Professional, 2004. Google ScholarDigital Library
- M. McCool, J. Reinders, and A. Robison, Structured Parallel Programming, 1st ed. San Francisco, CA, USA: Morgan Kaufmann Publishers Inc., 2012. Google ScholarDigital Library
- M. Danelutto and M. Torquati, "Structured parallel programming with "core" fastflow," in Central European Functional Programming School, ser. LNCS. Springer, 2015, vol. 8606, pp. 29--75.Google Scholar
- J. Enmyren and C. W. Kessler, "SkePU: A multi-backend skeleton programming library for multi-gpu systems," in Proceedings of the Fourth International Workshop on High-level Parallel Programming and Applications, ser. HLPP '10. New York, NY, USA: ACM, 2010, pp. 5--14. Google ScholarDigital Library
- S. Ernsting and H. Kuchen, "Algorithmic skeletons for multi-core, multi-gpu systems and clusters," Int. J. High Perform. Comput. Netw., vol. 7, no. 2, pp. 129--138, Apr. 2012. Google ScholarDigital Library
- C. Campbell and A. Miller, A Parallel Programming with Microsoft Visual C++: Design Patterns for Decomposition and Coordination on Multicore Architectures, 1st ed. Microsoft Press, 2011. Google ScholarDigital Library
- K. J. Brown, A. K. Sujeeth, H. J. Lee, T. Rompf, H. Chafi, M. Odersky, and K. Olukotun, "A heterogeneous parallel framework for domain-specific languages," in 2011 Inter. Conf. on Parallel Architectures and Compilation Techniques, ser. PACT '11. IEEE, 2011, pp. 89--100. Google ScholarDigital Library
- T. Sujeeth, Arvind K. and Rompf, K. J. Brown, H. Lee, H. Chafi, V. Popic, M. Wu, A. Prokopec, V. Jovanovic, M. Odersky, and K. Olukotun, Composition and Reuse with Compiled Domain-Specific Languages. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013, pp. 52--78. Google ScholarDigital Library
- M. Danelutto, J. D. Garcia, L. M. Sanchez, R. Sotomayor, and M. Torquati, "Introducing parallelism by using repara c++11 attributes," in 24th Euromicro Inter. Conf on Parallel, Distributed, and Network-Based Processing (PDP), Feb 2016, pp. 354--358. Google ScholarCross Ref
- M. Danelutto, T. D. Matteis, G. Mencagli, and M. Torquati, "Parallelizing high-frequency trading applications by using c++11 attributes," in 2015 IEEE Trustcom/BigDataSE/ISPA, vol. 3, Aug 2015, pp. 140--147. Google ScholarDigital Library
- M. Danelutto, T. De Matteis, G. Mencagli, and M. Torquati, "Data stream processing via code annotations," The Journal of Supercomputing, pp. 1--15, 2016. {Online}. Available Google ScholarDigital Library
- D. Chasapis, M. Casas, M. Moretó, R. Vidal, E. Ayguadé, J. Labarta, and M. Valero, "PARSECSs: Evaluating the impact of task parallelism in the parsec benchmark suite," ACM Trans. Archit. Code Optim., vol. 12, no. 4, pp. 41:1--41:22, Dec. 2015. Google ScholarDigital Library
- C. Bienia, S. Kumar, J. P. Singh, and K. Li, "The parsec benchmark suite: Characterization and architectural implications," in 17th Inter. Conf. on Parallel Architectures and Compilation Techniques, ser. PACT '08. ACM, 2008, pp. 72--81. Google ScholarDigital Library
- M. Aldinucci and M. Danelutto, "Stream parallel skeleton optimization," in Proc. of PDCS: Intl. Conf. on Parallel and Distributed Computing and Systems, IASTED. ACTA press, Nov. 1999, pp. 955--962.Google Scholar
- A. Sodani, R. Gramunt, J. Corbal, H. S. Kim, K. Vinod, S. Chinthamani, S. Hutsell, R. Agarwal, and Y. C. Liu, "Knights landing: Second-generation intel xeon phi product," IEEE Micro, vol. 36, no. 2, pp. 34--46, Mar 2016. Google ScholarDigital Library
Index Terms
- P3ARSEC: towards parallel patterns benchmarking
Recommendations
Bringing Parallel Patterns Out of the Corner: The P3 ARSEC Benchmark Suite
High-level parallel programming is an active research topic aimed at promoting parallel programming methodologies that provide the programmer with high-level abstractions to develop complex parallel software with reduced time to solution. Pattern-based ...
The correlation between parallel patterns and multi-core benchmarks
IWMSE '10: Proceedings of the 3rd International Workshop on Multicore Software EngineeringParallel Patterns can be thought of as standard solutions used to evaluate parallelism used in software. Multi-core benchmarks can be thought of as standard codes used for evaluating parallelism in hardware. In this document, we discuss the relationship ...
MINIME: Pattern-Aware Multicore Benchmark Synthesizer
We present a novel automated multicore benchmark synthesis framework with characterization and generation components. Our framework uses parallel patterns in capturing important characteristics of multi-threaded applications and generates synthetic ...
Comments