research-article

Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow

Authors:

Jason H. AndersonAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 10, Issue 2

Article No.: 11, Pages 1 - 23

https://doi.org/10.1145/3024063

Published: 06 April 2017 Publication History

Abstract

In this article, we consider implementing field-programmable gate arrays (FPGAs) using a standard cell design methodology and present a framework for the automated generation of synthesizable FPGA fabrics. The open-source Verilog-to-Routing (VTR) FPGA architecture evaluation framework [Rose et al. 2012] is extended to generate synthesizable Verilog for its in-memory FPGA architectural device model. The Verilog can subsequently be synthesized into standard cells, placed and routed using an ASIC design flow. A second extension to VTR generates a configuration bitstream for the FPGA, where the bitstream configures the FPGA to realize a user-provided placed and routed design. The proposed framework and methodology makes possible the silicon implementation of a wide range of VTR-modeled FPGA fabrics. In an experimental study, area and timing-optimized FPGA implementations in 65nm TSMC standard cells are compared to a 65nm Altera commercial FPGA. In addition, we consider augmenting the generic standard-cell library from TSMC with a manually designed and laid-out FPGA-specific cell. We demonstrate the utility of the custom cell in reducing the area of the synthesized FPGA fabric.

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Cited By

Nikolić SNikolić S(2025)IntroductionModern Programmable Interconnect Design10.1007/978-3-031-80629-2_1(1-9)Online publication date: 7-Mar-2025
https://doi.org/10.1007/978-3-031-80629-2_1
Biscontini APopovici ETemko A(2024)Machine Learning for FPGA Electronic Design AutomationIEEE Access10.1109/ACCESS.2024.351134512(182640-182662)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3511345
Gore GTang XGaillardon P(2023)A Scalable and Area-Efficient Configuration Circuitry for Semi-Custom FPGA DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.327044831:8(1128-1139)Online publication date: 1-Aug-2023
https://dl.acm.org/doi/10.1109/TVLSI.2023.3270448
Show More Cited By

Index Terms

Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Reconfigurable computing
2. Hardware
  1. Electronic design automation
    1. Hardware description languages and compilation

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Published In

cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 10, Issue 2

Special Section on Field Programmable Logic and Applications 2015 and Regular Papers

June 2017

133 pages

ISSN:1936-7406

EISSN:1936-7414

DOI:10.1145/3068424

Editor:
Steve Wilton
Department of Electrical and Computer Engineering / University of British Columbia / Kaiser 4112, 5500-2332 Main Mall / Vancouver, BC V6T 1Z4 Canada /

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Copyright © 2017 ACM.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 April 2017

Accepted: 01 November 2016

Revised: 01 October 2016

Received: 01 April 2016

Published in TRETS Volume 10, Issue 2

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Cited By

Nikolić SNikolić S(2025)IntroductionModern Programmable Interconnect Design10.1007/978-3-031-80629-2_1(1-9)Online publication date: 7-Mar-2025
https://doi.org/10.1007/978-3-031-80629-2_1
Biscontini APopovici ETemko A(2024)Machine Learning for FPGA Electronic Design AutomationIEEE Access10.1109/ACCESS.2024.351134512(182640-182662)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3511345
Gore GTang XGaillardon P(2023)A Scalable and Area-Efficient Configuration Circuitry for Semi-Custom FPGA DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.327044831:8(1128-1139)Online publication date: 1-Aug-2023
https://dl.acm.org/doi/10.1109/TVLSI.2023.3270448
Chung KDao NYu JKoch DAdler MIenne P(2022)How to Shrink My FPGAs — Optimizing Tile Interfaces and the Configuration Logic in FABulous FPGA FabricsProceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3490422.3502371(13-23)Online publication date: 13-Feb-2022
https://dl.acm.org/doi/10.1145/3490422.3502371
Qiu YCao YDai YYin WWang L(2022)TRAM: An Open-Source Template-based Reconfigurable Architecture Modeling Framework2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL57034.2022.00021(61-69)Online publication date: Aug-2022
https://doi.org/10.1109/FPL57034.2022.00021
SUZUKI DHANYU T(2021)Nonvolatile Field-Programmable Gate Array Using a Standard-Cell-Based Design FlowIEICE Transactions on Information and Systems10.1587/transinf.2020LOP0010E104.D:8(1111-1120)Online publication date: 1-Aug-2021
https://doi.org/10.1587/transinf.2020LOP0010
Nakazato YAmagasaki MZhao QIida MKuga M(2021)Automation of Domain-specific FPGA-IP Generation and TestProceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies10.1145/3468044.3468048(1-6)Online publication date: 21-Jun-2021
https://dl.acm.org/doi/10.1145/3468044.3468048
Gore GTang XGaillardon PLienig JBehjat LYang S(2021)A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAsProceedings of the 2021 International Symposium on Physical Design10.1145/3439706.3447047(135-142)Online publication date: 22-Mar-2021
https://dl.acm.org/doi/10.1145/3439706.3447047
Bao BAnderson J(2021)Dynamic Power Analysis of Standard-Cell FPGA Fabrics2021 IEEE 34th International System-on-Chip Conference (SOCC)10.1109/SOCC52499.2021.9739496(182-187)Online publication date: 14-Sep-2021
https://doi.org/10.1109/SOCC52499.2021.9739496
Razzaq AYe A(2021)Static power model for CMOS and FPGA circuitsIET Computers & Digital Techniques10.1049/cdt2.1202115:4(263-278)Online publication date: 23-Mar-2021
https://doi.org/10.1049/cdt2.12021
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