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Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS

Published: 24 January 2017 Publication History

Abstract

Embedded systems for Internet-of-Things applications present new challenges to system design. From a hardware design perspective, energy efficiency is paramount, as most of devices have a limited power supply due to size considerations. Transmitting data away from the node remains a very power hungry operation, and the only viable solution to this problem is to reduce the amount of data by performing pre-processing which again requires additional computational power. Hence modern embedded devices need to strike a fine balance between the power needed for acquisition/processing and communication. In many scenarios, small IoT devices will be deployed widely making them vulnerable to malicious attacks. Thus, for practical applications, these devices also need to fit the necessary resources to provide adequate security services.
We present a cryptographic hardware accelerator capable of supporting multiple encryption and decryption modes for different cryptographic algorithms (AES, Keccak) in an energy efficient multi-core cluster optimized for embedded digital signal processing applications implemented in 65 nm CMOS technology. We show that it is possible to have the necessary computation power to perform cryptographic services in addition to state of the art processing in a power budget that is compatible with IoT devices in a mature 65 nm CMOS technology. When running at 0.8 V the SoC with the cryptographic accelerator can be clocked at 84 MHz running AES-XTS at more than 250 Mbits/s consuming a total of 27 mW, which is a 100 × gain in energy and 496 × gain in operation speed over an optimized software implementation running on a single 32 bit OpenRISC core.

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Cited By

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  • (2021)A RISC-V in-network accelerator for flexible high-performance low-power packet processingProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00079(958-971)Online publication date: 14-Jun-2021
  • (2020)Privacy Attack On IoT: a Systematic Literature Review2020 International Conference on ICT for Smart Society (ICISS)10.1109/ICISS50791.2020.9307568(1-8)Online publication date: 19-Nov-2020

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cover image ACM Other conferences
CS2 '17: Proceedings of the Fourth Workshop on Cryptography and Security in Computing Systems
January 2017
39 pages
ISBN:9781450348690
DOI:10.1145/3031836
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 24 January 2017

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Author Tags

  1. AES
  2. VLSI design
  3. embedded systems
  4. hardware cryptography

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  • Research-article

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  • Nano-Tera.ch

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CS2 '17

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CS2 '17 Paper Acceptance Rate 4 of 11 submissions, 36%;
Overall Acceptance Rate 27 of 91 submissions, 30%

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View all
  • (2021)A RISC-V in-network accelerator for flexible high-performance low-power packet processingProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00079(958-971)Online publication date: 14-Jun-2021
  • (2020)Privacy Attack On IoT: a Systematic Literature Review2020 International Conference on ICT for Smart Society (ICISS)10.1109/ICISS50791.2020.9307568(1-8)Online publication date: 19-Nov-2020

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