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Improving Detailed Routability and Pin Access with 3D Monolithic Standard Cells

Published: 19 March 2017 Publication History

Abstract

We study the impact of using 3D monolithic (3DM) standard cells on improving detailed routability and pin access. We propose a design flow which transforms standard rows of single-tier "2D" cells into rows of standard 3DM cells folded into two tiers. The transformation preserves layout characteristics such as overall area and number of metal layers for signal routing (i.e., M2 and above). It also creates redundant pins and free routing tracks in the two tiers used by the 3DM cells. We then propose an Integer Linear Program which routes as many nets as possible on the free 3DM routing tracks, leaving the rest of the nets to be routed via a standard global and detailed router on the metal layers dedicated for signal routing. Our experiments show significant improvement in detailed routability metrics using 3DM cells compared to using 2D standard cells.

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Cited By

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  • (2020)Grid-based Framework for Routability Analysis and Diagnosis with Conditional Design RulesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.2977066(1-1)Online publication date: 2020
  • (2019)Morphed Standard Cell Layouts for Pin Length Reduction2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2019.00025(94-99)Online publication date: Jul-2019
  • (2018)Fast and precise routability analysis with conditional design rulesProceedings of the 20th System Level Interconnect Prediction Workshop10.1145/3225209.3225210(1-8)Online publication date: 23-Jun-2018
  • Show More Cited By

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    cover image ACM Conferences
    ISPD '17: Proceedings of the 2017 ACM on International Symposium on Physical Design
    March 2017
    176 pages
    ISBN:9781450346962
    DOI:10.1145/3036669
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 19 March 2017

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    Author Tags

    1. 3d monolithic
    2. 3d vlsi
    3. detailed routability
    4. pin access
    5. standard cells

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    ISPD '17: International Symposium on Physical Design
    March 19 - 22, 2017
    Oregon, Portland, USA

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    Overall Acceptance Rate 62 of 172 submissions, 36%

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    International Symposium on Physical Design
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    Cited By

    View all
    • (2020)Grid-based Framework for Routability Analysis and Diagnosis with Conditional Design RulesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.2977066(1-1)Online publication date: 2020
    • (2019)Morphed Standard Cell Layouts for Pin Length Reduction2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2019.00025(94-99)Online publication date: Jul-2019
    • (2018)Fast and precise routability analysis with conditional design rulesProceedings of the 20th System Level Interconnect Prediction Workshop10.1145/3225209.3225210(1-8)Online publication date: 23-Jun-2018
    • (2018)A Comparative Study of Local Net Modeling Using Machine LearningProceedings of the 2018 Great Lakes Symposium on VLSI10.1145/3194554.3194579(273-278)Online publication date: 30-May-2018
    • (2017)Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy IntegrationIPSJ Transactions on System LSI Design Methodology10.2197/ipsjtsldm.10.4510(45-62)Online publication date: 2017

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