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Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning

Published: 19 March 2017 Publication History

Abstract

Design rule check (DRC) violations after detailed routing prevent a design from being taped out. To solve this problem, state-of-the-art commercial EDA tools global-route the design to produce a global-route congestion map; this map is used by the placer to optimize the placement of the design to reduce detailed-route DRC violations. However, in sub-14nm processes and beyond, DRCs arising from multiple patterning and pin-access constraints drastically weaken the correlation between global-route congestion and detailed-route DRC violations. Hence, the placer|based on the global-route congestion map|may leave too many detailed-route DRC violations to be fixed manually by designers. In this paper, we present a method that employs (1) machine-learning techniques to effectively predict detailed-route DRC violations after global routing and (2) detailed placement techniques to effectively reduce detailed-route DRC violations. We demonstrate on several layouts of a sub-14nm industrial design that this method predicts the locations of 74% of the detailed-route DRCs (with false positive prediction rate below 0.2%) and automatically reduces the number of detailed-route DRC violations by up to 5x. Whereas previous works on machine learning for routability [30] [4] have focused on routability prediction at the floorplanning and placement stages, ours is the first paper that not only predicts the actual locations of detailed-route DRC violations but furthermore optimizes the design to significantly reduce such violations.

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  • (2024)Artificial Neural Network-based Prediction and Alleviation of Congestion during Placement2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)10.1109/VLSID60093.2024.00056(300-305)Online publication date: 6-Jan-2024
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cover image ACM Conferences
ISPD '17: Proceedings of the 2017 ACM on International Symposium on Physical Design
March 2017
176 pages
ISBN:9781450346962
DOI:10.1145/3036669
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 19 March 2017

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Author Tags

  1. advanced node
  2. chip design
  3. design-violation check
  4. machine learning
  5. physical design
  6. placement and route
  7. routability
  8. vlsi

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ISPD '17: International Symposium on Physical Design
March 19 - 22, 2017
Oregon, Portland, USA

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Cited By

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  • (2025)Eh-DRVP: Combining placement and global routing data in a hyper-image-based DRV predictorIntegration10.1016/j.vlsi.2024.102309101(102309)Online publication date: Mar-2025
  • (2024)Integrating Operations Research into Very Large-Scale Integrated Circuits Placement Design: A ReviewAsia-Pacific Journal of Operational Research10.1142/S021759592450007641:06Online publication date: 6-Jul-2024
  • (2024)Artificial Neural Network-based Prediction and Alleviation of Congestion during Placement2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)10.1109/VLSID60093.2024.00056(300-305)Online publication date: 6-Jan-2024
  • (2024)Decap Insertion With Local Cell Relocation Minimizing IR-Drop Violations and Routing DRVsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.336451932:5(823-834)Online publication date: May-2024
  • (2024)Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction for Designs in Advanced Technology Nodes With Consolidated Practical Applicability and SustainabilityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.340589443:12(4786-4799)Online publication date: Dec-2024
  • (2024)Toward Fully Automated Machine Learning for Routability Estimator DevelopmentIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.333081843:3(970-982)Online publication date: Mar-2024
  • (2024)Migrating Standard Cells for Multiple Drive Strengths by Routing Imitation2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617650(5-10)Online publication date: 10-May-2024
  • (2024)Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm NodeIEEE Access10.1109/ACCESS.2024.342733212(97557-97571)Online publication date: 2024
  • (2024)Machine learning optimal ordering in global routing problems in semiconductorsScientific Reports10.1038/s41598-024-82226-914:1Online publication date: 28-Dec-2024
  • (2024)Performance Evaluation of GA, HS, PSO Algorithms for Optimizing Area, Wirelength Using MCNC ArchitecturesModern Approaches in Machine Learning and Cognitive Science: A Walkthrough10.1007/978-3-031-43009-1_5(53-70)Online publication date: 14-Jan-2024
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