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An FPGA Solver for Partial MaxSAT Problems Based on Stochastic Local Search

Published:11 January 2017Publication History
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Abstract

In this paper, we propose an FPGA solver for partial maximum satisfiability (PMS) problems based on the Dist algorithm, which is one of the best performing stochastic local search algorithms for PMS problems. The Dist algorithm searches for a truth assignment for the variables that satisfies all of the hard clauses and as many soft clauses as possible by iteratively selecting a variable using a heuristic and flipping its truth value. During each iteration, new candidate variables for flipping are generated and existing ones may disappear. In our solver, the variables that may become new candidates for flipping are evaluated by parallel and pipeline processing, and then only the variables that actually become the candidates for flipping are extracted and gathered up in concurrent with the pipeline processing. The extraction process is not influenced by the number of the new candidates or their random generation, which minimizes the disturbance of the parallel and pipeline processing. Our FPGA solver can solve large PMS problems up to 7.74 times faster than running Dist on CPU.

References

  1. S. Cai, C. Luo, J. Thoronton and K. Su, "Tailoring Local Search for Partial MaxSAT", AAAI-14, pp. 2623--2629, 2014. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. B. Selman, H. Kautz and B. Cohen, "Noise Strategies for Improving Local Search", AAAI-94, pp. 337--343, 1994. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. D. McAllester, B. Selman and H. Kautz, "Evidence for Invariants in Local Search", AAAI-97, pp. 321--326, 1997. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. R. Yap, S. Wang and M. Henz, "Real-time Reconfigurable Hardware WSAT Variants", FPL-2003, pp. 488--496, 2003.Google ScholarGoogle Scholar
  5. K. Kanazawa and T. Maruyama, "An Approach for Solving Large SAT Problems on FPGA", Trans. ACM-TRETS Vol.4, No.1, Article 10, pp.1--pp.21, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. K. Kanazawa and T. Maruyama, "FPGA Acceleration of SAT/MaxSAT Solving using Variable-way Cache", FPL-14, pp.1--4, 2014.Google ScholarGoogle Scholar
  7. "Ninth MaxSAT Evaluation", http://www.maxsat.udl.cat/14/Google ScholarGoogle Scholar

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  • Published in

    cover image ACM SIGARCH Computer Architecture News
    ACM SIGARCH Computer Architecture News  Volume 44, Issue 4
    HEART '16
    September 2016
    96 pages
    ISSN:0163-5964
    DOI:10.1145/3039902
    Issue’s Table of Contents

    Copyright © 2017 Authors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    • Published: 11 January 2017

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