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Deadline-Aware Joint Optimization of Sleep Transistor and Supply Voltage for FinFET Based Embedded Systems

Published: 10 May 2017 Publication History

Abstract

Leakage power consumption has recently become a great concern for modern embedded systems. FinFET technologies, power gating, and near- and super-threshold regimes can significantly reduce the power consumption. However, there lacks a comprehensive analysis of jointly applying the aforementioned power saving techniques. In this paper, we investigate the application of power gating to FinFET circuits operating in near- and super-threshold voltage regimes for embedded system applications. A joint optimization algorithm is proposed to determine the width/length, position and threshold type of the sleep transistor together with the operating voltage constrained to a certain deadline, and with the goal of minimizing energy per operation. Experimental results demonstrate that the proposed algorithm achieves up to 99.9% energy reductions when compared to the near-threshold approach without power gating and 95.3% when compared to deadline-free optimization.

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  1. Deadline-Aware Joint Optimization of Sleep Transistor and Supply Voltage for FinFET Based Embedded Systems

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    cover image ACM Conferences
    GLSVLSI '17: Proceedings of the Great Lakes Symposium on VLSI 2017
    May 2017
    516 pages
    ISBN:9781450349727
    DOI:10.1145/3060403
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    Published: 10 May 2017

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    Author Tags

    1. algorithm
    2. near-threshold computing
    3. power gating

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    May 10 - 12, 2017
    Alberta, Banff, Canada

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    GLSVLSI '17 Paper Acceptance Rate 48 of 197 submissions, 24%;
    Overall Acceptance Rate 312 of 1,156 submissions, 27%

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