ABSTRACT
This paper provides a systematization of knowledge in the domain of integrated circuit protection through obfuscation with a focus on the recent Boolean satisfiability (SAT) attacks. The study systematically combines real-world IC reverse engineering reports, experimental results using the most recent oracle-guided attacks, and concepts in machine-learning and cryptography to draw a map of the state-of-the-art of IC obfuscation and future challenges and opportunities.
- Chipwork. http://ww.chipworks.com/.Google Scholar
- J. L. Balcázar, J. Castro, D. Guijarro, J. Köbler, and W. Lindner. A general dimension for query learning. Journal of Computer and System Sciences, 73(6):924--940, 2007. Google ScholarDigital Library
- B. Barak, O. Goldreich, R. Impagliazzo, S. Rudich, A. Sahai, S. Vadhan, and K. Yang. On the (im) possibility of obfuscating programs. In Annual International Cryptology Conference, pages 1--18. Springer, 2001. Google ScholarDigital Library
- J. Baukus, L. Chow, and W. Clark. Permanently on transistor implemented using a double polysilicon layer cmos process with buried contact, May 25 2004. US Patent 6,740,942.Google Scholar
- J. Baukus, L. Chow, and W. Clark. Programmable connector/isolator and double polysilicon layer cmos process with buried contact using the same, May 17 2005. US Patent 6,893,916.Google Scholar
- J. P. Baukus, W. M. Clark Jr, L.-W. Chow, and A. R. Kramer. Integrated circuit security system and method with implanted interconnections, Feb. 2 1999. US Patent 5,866,933.Google Scholar
- A. C. Baumgarten. Preventing integrated circuit piracy using reconfigurable logic barriers. 2009.Google Scholar
- R. Chakraborty and S. Bhunia. HARPOON: An obfuscation-based soc design methodology for hardware protection. IEEE J. Technol. Comput. Aided Design, 28(10):1493--1502, 2009. Google ScholarDigital Library
- S. Chen, J. Chen, D. Forte, J. Di, M. Tehranipoor, and L. Wang. Chip-level anti-reverse engineering using transformable interconnects. In Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems, pages 109--114. IEEE, 2015.Google ScholarCross Ref
- L. Chow, J. Baukus, and W. Clark. Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations, Sept. 14 2004. US Patent 6,791,191.Google Scholar
- L. Chow, J. Baukus, and W. Clark. Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide, Nov. 13 2007. US Patent 7,294,935.Google Scholar
- L.-W. Chow, J. P. Baukus, and W. M. Clark Jr. Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide, Nov. 13 2007. US Patent 7,294,935.Google Scholar
- L. W. Chow, J. P. Baukus, B. J. Wang, and R. P. Cocchi. Camouflaging a standard cell based integrated circuit, Apr. 3 2012. US Patent 8,151,235.Google Scholar
- L.-W. Chow, W. M. Clark Jr, and J. P. Baukus. Covert transformation of transistor properties as a circuit protection method. US Patent 7,217,977.Google Scholar
- R. P. Cocchi, J. P. Baukus, L. W. Chow, and B. J. Wang. Circuit camouflage integration for hardware ip protection. In Proc. Design Automation Conf., pages 1--5. IEEE, 2014. Google ScholarDigital Library
- S. Dupuis, P.-S. Ba, G. Di Natale, M.-L. Flottes, and B. Rouzeyre. A novel hardware logic encryption technique for thwarting illegal overproduction and hardware trojans. In Proc. IEEE Int. On-Line Testing Symposium, pages 49--54. IEEE, 2014.Google ScholarCross Ref
- M. El Massad, S. Garg, and M. V. Tripunitara. Integrated circuit (ic) decamouflaging: Reverse engineering camouflaged ics within minutes. In NDSS, 2016.Google Scholar
- F. Koushanfar. Provably secure active ic metering techniques for piracy avoidance and digital rights management. IEEE Trans. on Information Forensics and Security, 7(1):51--63, 2012. Google ScholarDigital Library
- I. Kuon and J. Rose. Measuring the gap between fpgas and asics. 26(2):203--215, 2007. Google ScholarDigital Library
- D. D. Lewis and J. Catlett. Heterogeneous uncertainty sampling for supervised learning. In Proc. Int. Conf. on Machine Learning, pages 148--156, 1994. Google ScholarDigital Library
- M. Li, K. Shamsi, T. Meade, Z. Zhao, B. Yu, Y. Jin, and D. Z. Pan. Provably secure camouflaging strategy for ic protection. In ICCAD, page 28. ACM, 2016. Google ScholarDigital Library
- B. Liu and B. Wang. Embedded reconfigurable logic for asic design obfuscation against supply chain attacks. In Proc. Design, Automation and Test in Eurpoe, pages 1--6, 2014. Google ScholarDigital Library
- B. Liu and B. Wang. Reconfiguration-based vlsi design for security. 5(1):98--108, 2015.Google Scholar
- J. T. McDonald, Y. Kim, and D. Koranek. Deterministic circuit variation for anti-tamper applications. In Proceedings of the Seventh Annual Workshop on Cyber Security and Information Intelligence Research, page 68. ACM, 2011. Google ScholarDigital Library
- T. Olivier and N. Dmitry. On the impact of automating the ic analysis process. In Blackhat USA, 2015.Google Scholar
- J. Parham, Y. Kim, et al. Hiding circuit components using boundary blurring techniques. In Proc. of IEEE Annual Symposium on VLSI, pages 5--7, 2010.Google Scholar
- J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri. Security analysis of logic obfuscation. In DAC, pages 83--89, 2012. Google ScholarDigital Library
- J. Rajendran, M. Sam, O. Sinanoglu, and R. Karri. Security analysis of integrated circuit camouflaging. In Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security, pages 709--720. ACM, 2013. Google ScholarDigital Library
- J. Rajendran, O. Sinanoglu, and R. Karri. Regaining trust in vlsi design: Design-for-trust techniques. Proceedings of the IEEE, 102(8):1266--1282, 2014.Google ScholarCross Ref
- J. Rajendran, H. Zhang, C. Zhang, G. S. Rose, Y. Pino, O. Sinanoglu, and R. Karri. Fault analysis-based logic encryption. IEEE Trans. on Computers, 64(2):410--424, 2015.Google ScholarCross Ref
- J. A. Roy, F. Koushanfar, and I. L. Markov. Epic: Ending piracy of integrated circuits. In Proc. Design, Automation and Test in Eurpoe, DATE '08, pages 1069--1074, 2008. Google ScholarDigital Library
- J. A. Roy, F. Koushanfar, and I. L. Markov. Protecting bus-based hardware ip by secret sharing. In Proceedings of the 45th annual Design Automation Conference, pages 846--851. ACM, 2008. Google ScholarDigital Library
- S. K. Saha. Emerging business trends in the microelectronics industry. Open Journal of Business and Management, 4(01):105, 2015.Google ScholarCross Ref
- K. Shamsi, M. Li, T. Meade, Z. Zhao, Y. Jin, and D. Z. Pan. Appsat: Approximately deobfuscating integrated circuits. In Proc. IEEE Symp. Hardware-Oriented Security and Trust. IEEE, 2017.Google ScholarCross Ref
- K. Shamsi, M. Li, T. Meade, Z. Zhao, Y. Jin, and D. Z. Pan. Cyclic obfuscation for creating sat-unresolvable circuits. In Proc. Great Lake Symp. on VLSI. IEEE, 2017. Google ScholarDigital Library
- M. Shiozaki, R. Hori, and T. Fujino. Diffusion programmable device: The device to prevent reverse engineering. IACR Cryptology ePrint Archive, 2014:109, 2014.Google Scholar
- P. Subramanyan, S. Ray, and S. Malik. Evaluating the security of logic encryption algorithms. In Proc. IEEE Symp. Hardware-Oriented Security and Trust, pages 137--143. IEEE, 2015.Google ScholarCross Ref
- P. Subramanyan, N. Tsiskaridze, W. Li, A. Gascon, W. Y. Tan, A. Tiwari, N. Shankar, S. Seshia, and S. Malik. Reverse engineering digital circuits using structural and functional analyses. IEEE Trans. on Emerging Topics in Computing, 2(1):63--80, 2014.Google ScholarCross Ref
- R. Torrance and D. James. The state-of-the-art in ic reverse engineering. In Cryptographic Hardware and Embedded Systems, pages 363--381. Springer, 2009. Google ScholarDigital Library
- R. Torrance and D. James. The state-of-the-art in semiconductor reverse engineering. In Proc. Design Automation Conf. ACM, 2011. Google ScholarDigital Library
- A. Vijayakumar, V. C. Patil, D. E. Holcomb, C. Paar, and S. Kundu. Physical design obfuscation of hardware: A comprehensive investigation of device and logic-level techniques. IEEE Transactions on Information Forensics and Security, 12(1):64--77, 2017. Google ScholarDigital Library
- T. Winograd, H. Salmani, H. Mahmoodi, K. Gaj, and H. Homayoun. Hybrid stt-cmos designs for reverse-engineering prevention. In Proc. Design Automation Conf., page 88. ACM, 2016. Google ScholarDigital Library
- T. F. Wu, K. Ganesan, A. Hu, H.-S. P. Wong, S. Wong, and S. Mitra. Tpad: Hardware trojan prevention and detection for trusted integrated circuits, 2015.Google Scholar
- Y. Xie and A. Srivastava. Mitigating sat attack on logic locking. http://eprint.iacr.org/2016/590.pdf.Google Scholar
- M. Yasin, B. Mazumdar, J. Rajendran, and O. Sinanoglu. Sarlock: Sat attack resistant logic locking. In Proc. IEEE Symp. Hardware-Oriented Security and Trust, pages 236--241, 2016.Google ScholarCross Ref
- M. Yasin, B. Mazumdar, O. Sinanoglu, and J. Rajendran. Security analysis of anti-sat. https://eprint.iacr.org/2016/896.pdf.Google Scholar
- M. Yasin, B. Mazumdar, O. Sinanoglu, and J. Rajendran. Camoperturb: secure ic camouflaging for minterm protection. In Proc. Int. Conf. on Computer Aided Design, page 29. ACM, 2016. Google ScholarDigital Library
- M. Yasin, J. J. Rajendran, O. Sinanoglu, and R. Karri. On improving the security of logic locking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 35(9):1411--1424, 2016.Google ScholarDigital Library
Index Terms
- Circuit Obfuscation and Oracle-guided Attacks: Who can Prevail?
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