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A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications

Published: 18 June 2017 Publication History

Abstract

Current and future applications impose high demands on software-defined radio (SDR) platforms in terms of latency, reliability, and flexibility. This paper presents a heterogeneous SDR MPSoC with a hexagonal network-on-chip to address these issues. It features four data processing modules and a baseband processing engine for iterative multiple-input multiple-output (MIMO) receiving. Integrated memory controllers enable dynamic data flow mapping and application isolation. In a 4 x 4 MIMO application scenario, the MPSoC achieves a throughput of 232 Mbit/s with a latency of 20 μs while consuming 414 mW. It outperforms state-of-the-art platforms in terms of throughput by a factor of 4.

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cover image ACM Conferences
DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017
June 2017
533 pages
ISBN:9781450349277
DOI:10.1145/3061639
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 18 June 2017

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Cited By

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  • (2022)Accurate Estimation of Service Rates in Interleaved Scratchpad Memory SystemsACM Transactions on Embedded Computing Systems10.1145/345717121:1(1-15)Online publication date: 10-Feb-2022
  • (2022)AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V ProcessorsIEEE Access10.1109/ACCESS.2022.316868610(43895-43913)Online publication date: 2022
  • (2022)Tagged Geometric History Length Access Interval Prediction for Tightly Coupled Memory SystemsEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-031-15074-6_6(90-100)Online publication date: 3-Jul-2022
  • (2021)Efficient Communication Protection of Many-Core Systems against Active AttackersElectronics10.3390/electronics1003023810:3(238)Online publication date: 21-Jan-2021
  • (2020)Slicing FIFOs for On-Chip Memory Bandwidth ExhaustionIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2019.292613467:2(441-450)Online publication date: Feb-2020
  • (2020)Modem Design in the Era of 5G and Beyond: The Need for a Formal Approach2020 27th International Conference on Telecommunications (ICT)10.1109/ICT49546.2020.9239539(1-5)Online publication date: 5-Oct-2020
  • (2020)Towards a Modular RISC-V Based Many-Core Architecture for FPGA AcceleratorsIEEE Access10.1109/ACCESS.2020.30157068(148812-148826)Online publication date: 2020
  • (2019)M3XProceedings of the 2019 USENIX Conference on Usenix Annual Technical Conference10.5555/3358807.3358859(617-631)Online publication date: 10-Jul-2019
  • (2019)Queue Based Memory Management Unit for Heterogeneous MPSoCs2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8715129(1297-1300)Online publication date: Mar-2019
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