Sunil P. Khatri
- 1."The National Tecnology Roadmap for Semiconductors." http ://notes. sematech, org/97melec, htm, 1997.Google Scholar
- 2.R D. Fisher, "Clock Cycle Estimation for Future Microprocessor Generations," tech. rep., SEMATECH, 1997.Google Scholar
- 3."Physical Design Modelling and Verification Project (SPACE Project)." http ://cas. et. tudelft, nl/research/space/html.Google Scholar
- 4.B. A. Oieseke et al., "A 600MHz Superscalar RISC Microprocessor with Out-of- Order Execution," in Digest of Technical Papers, International Solid State Circuits Conference, 1997.Google Scholar
- 5.A. Rubio, N. Itazaki, and K. Kinoshita, "An approach to the analysis and detection of cross-talk faults in digital VLSI circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, pp. 387-95, March 1994.Google ScholarDigital Library
- 6.D. Kirkpatrick and A. Sangiovanni-Vincentelli, "Digital Sensitivity: Predicting signal interaction using functional analysis," in P~vceedings of the International Conference on Computer-Aided Design, pp. 536-41, Nov 1996. Google ScholarDigital Library
- 7.D. Kirkpatrick and A. Sangiovanni-Vincentelli, "Techniques for cross-talk avoidance in the physical design of high-performance digital systems," in P~vceedings of the International Conference on Computer-Aided Design, pp. 616-9, Nov 1994. Google ScholarDigital Library
- 8.S.Y. Liao, Miclvwave Devices and Circuits. Prentice-Hall, 1980.Google Scholar
- 9."Analysis of Silicon Inductors and Transformers for ICs." http ://kabuki. eecs. berkeley, edu/~nikne j ad/doc/asiticxloc, html.Google Scholar
- 10.R.K. Brayton, "Logic Synthesis for Ultra Deep Sub-Micron (UDSM)," in Proceedings of the 35th Design Automation Conference, 1998.Google Scholar
- 11.J. Reed, M. Santomauro, and A. Sangiovanni-Vincentelli, "A new gridless channel router: Yet another channel router the second (YACR-II)," in Digest of Technical Papers International Conference on Computer-Aided Design, 1984.Google Scholar
- 12.G.T. Hamachi, R. N. Mayo, and J. K. Ousterhout, "Magic: A VLSI Layout system," in 21st Design Automation Conference P1vceedings, 1984. Google ScholarDigital Library
- 13.E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, R R. Stephan, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "SIS: A System for Sequential Circuit Synthesis," Tech. Rep. UCB/ERL M92/41, Electronics Research Laboratory, Univ. of California, Berkeley, CA 94720, May 1992.Google Scholar
- 14.A. Casotto, ed., Octtools-5.1 Manuals, (Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA 94720), University of Calitbrnia at Berkeley, Sept. 1991.Google Scholar
- 15.C. Sechen and A. Sangiovanni-Vincentelli, "The TimberWolf Placement and Routing Package," IEEE Journal of Solid-State Ci~vuits, 1985.Google ScholarCross Ref
- 16.D. Sylvester and K. Keutzer, "Getting to the bottom of deep submicron," in P~vceedings of the International Conference on Computer-Aided Design, 1998. To Appear. Google ScholarDigital Library
- 17.S. Yamashita, H. Sawada, and A. Nagoya, "A new method to express functional permissibilities for LUT based FPGAs and its applications," in P~vceedings of the International Conference on Computer-Aided Design, 1996. Google ScholarDigital Library
- 18.R. Brayton, "Understanding SPFDs: A new method for specifying flexibility," in Workshop Notes, International Workshop on Logic Synthesis, 1997.Google Scholar
Index Terms
- A novel VLSI layout fabric for deep sub-micron applications
Recommendations
Deep sub micron high aspect ratio polymer structures produced by hard X-ray lithography
Microfabrication using X-ray lithography is a well established process in many laboratories worldwide. Radiation spectra, mask technology and process conditions are optimized for patterning resist thicknesses of several hundred micrometers with lateral ...
Fabrication sub-micron gratings based on embossing
DTIP '03: Proceedings of the Symposium on Design, Test, Integration and Packaging of MEMS/MOEMSWe demonstrated two kinds of sub-micron gratings fabricated by embossing method from anisotropically etched silicon molds. One kind of grating is a line grating with a pitch of 500 nm; the other kind is grating array with a pitch of 200 nm. We ...
Resistless patterning of sub-micron structures by evaporation through nanostencils
We describe a sub-micron shadow-mask evaporation or nanostencil technique for single-layer material patterning. The technique does not involve photoresist processing steps and is therefore applicable on arbitrary surfaces. It allows for rapid ...
Comments