Operating CMOS circuits at subthreshold supply voltages is an attractive solution for substantial energy reduction, at the expense of strong timing performance degradation, for a broad range of battery operated appliances. One of the challenges of this approach in current technology nodes is the reduced available noise margin when operating at low supplies. This paper evaluates the Static Noise Margin (SNM) to ensure reliable estimations in subthreshold CMOS circuits. The evaluation starts with a DC simulation of cells, providing a guideline on how its inputs should be stressed. The analysis shows that improperly employing the DC simulation may lead up to 70% worst results, thereby underestimating the SNM. The DC simulation methodology was applied herein to three different techniques, to identify which can reduce the SNM pessimism without overestimating. To extended the range of assessment, and to allow more accurate results, Monte Carlo simulations are used to evaluate the impact of both process and temperature variations on SNM for 15 different pairs (combinations) of CMOS logic cells. Results suggest that the maximum-square technique to define SNM is the most suitable for CMOS logic circuit operating in subthreshold. Those methods are validated through extensive simulation experiments with cells in a 65-nm CMOS bulk technology.