Cited By
View all- Hsia SWang SKuo T(2023)VLSI architecture and implementation of HDR camera signal processorJournal of Real-Time Image Processing10.1007/s11554-023-01262-220:1Online publication date: 30-Jan-2023
This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high-level hardware design and efficient hardware implementation. The central idea of this framework is the integration of ...
We present a novel compression scheme for high dynamic range textures, targeted for hardware implementation. Our method encodes images at a constant 8 bits per pixel, for a compression ratio of 6:1. We demonstrate that our method achieves good visual ...
We present a novel compression scheme for high dynamic range textures, targeted for hardware implementation. Our method encodes images at a constant 8 bits per pixel, for a compression ratio of 6:1. We demonstrate that our method achieves good visual ...
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