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Segmented spline hardware design for high dynamic range video pre-processor

Published: 28 August 2017 Publication History

Abstract

Digital video capturing generates a huge amount of data to be processed and stored, which requires the use of compression techniques. Efficient hardware designs for real-time encoding are mandatory, especially for embedded systems, due to their performance and energy constraints. High Dynamic Range (HDR) video is a new technology that tends to be present in the next generation of devices in order to improve the video quality. However, the particularities of this kind of video incur in increased data to be stored and require support for special features in video processors/codecs. The current approach includes a pre-processor annex to an encoder to convert the HDR videos to a format that can be handled. This work presents a hardware design for the most time-consuming process within the HDR pre-processor, the Segmented Spline. The hardware design was developed based on hardware-oriented mathematical simplifications of the Segmented Spline, which reduce about 50% the number of basic operators. The developed architecture was synthesized for an Altera Stratix V FPGA, and the synthesis results show the optimized hardware can work at 17.56MHz using approximately 11k ALMs.

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  • (2023)VLSI architecture and implementation of HDR camera signal processorJournal of Real-Time Image Processing10.1007/s11554-023-01262-220:1Online publication date: 30-Jan-2023

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cover image ACM Conferences
SBCCI '17: Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands
August 2017
238 pages
ISBN:9781450351065
DOI:10.1145/3109984
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 28 August 2017

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Author Tags

  1. hardware
  2. high dynamic range
  3. pre-processor
  4. segmented spline

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SBCCI '17
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SBCCI '17: 30th Symposium on Integrated Circuits and Systems Design
August 28 - September 1, 2017
Ceará, Fortaleza, Brazil

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Overall Acceptance Rate 133 of 347 submissions, 38%

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  • (2023)VLSI architecture and implementation of HDR camera signal processorJournal of Real-Time Image Processing10.1007/s11554-023-01262-220:1Online publication date: 30-Jan-2023

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