Lester Kalms
ABSTRACT
Feature detection is a major operation in various computer vision systems. The KAZE algorithm and its improved version, Accelerated-KAZE (AKAZE), are considered as the first algorithms to detect features by building a scale space using nonlinear diffusion. However, the detection part of the algorithm achieves only 6 fps on an Intel Core i7-4790 processor for an image resolution of 1024x768. This work proposes a pipelined architecture for a hardware accelerator that performs the AKAZE detection algorithm. Firstly, modifications are done to the original algorithm to reduce the amount of computations and memory accesses. Then, the accelerator is implemented on a Xilinx Zynq SoC and achieves 98 fps for the same resolution and a frequency of 100 MHz. Compared to the original algorithm, the design has an error in average inliers ratio by only 4%.
- 2004. Visual Geometry Group Home Page. (2004). Retrieved February 20, 2017 from http://www.robots.ox.ac.uk/~vgg/data/data-aff.htmlGoogle Scholar
- 2014. ZedBoard HW Users Guide. (2014). Retrieved February 20, 2017 from http://zedboard.org/sites/default/files/documentations/ZedBoard_HW_UG_v2_2.pdfGoogle Scholar
- A. Alahi, R. Ortiz, and P. Vandergheynst. 2012. FREAK: Fast Retina Keypoint. In 2012 IEEE Conference on Computer Vision and Pattern Recognition. 510--517. https://doi.org/10.1109/CVPR.2012.6247715 Google ScholarCross Ref
- Pablo Fernández Alcantarilla, Adrien Bartoli, and Andrew J. Davison. 2012. KAZE Features. Springer Berlin Heidelberg, Berlin, Heidelberg, 214--227. https://doi.org/10.1007/978-3-642-33783-3_16 Google ScholarDigital Library
- Herbert Bay, Tinne Tuytelaars, and Luc Van Gool. 2006. SURF: Speeded Up Robust Features. Springer Berlin Heidelberg, Berlin, Heidelberg, 404--417. https://doi.org/10.1007/11744023_32 Google ScholarDigital Library
- Michael Calonder, Vincent Lepetit, Christoph Strecha, and Pascal Fua. 2010. BRIEF: Binary Robust Independent Elementary Features. Springer Berlin Heidelberg, Berlin, Heidelberg, 778--792. https://doi.org/10.1007/978-3-642-15561-1_56 Google ScholarCross Ref
- L. C. Chiu, T. S. Chang, J. Y. Chen, and N. Y. C. Chang. 2013. Fast SIFT Design for Real-Time Visual Feature Extraction. IEEE Transactions on Image Processing 22, 8 (Aug 2013), 3158--3167. https://doi.org/10.1109/TIP.2013.2259841 Google ScholarCross Ref
- F. C. Huang, S. Y. Huang, J. W. Ker, and Y. C. Chen. 2012. High-Performance SIFT Hardware Accelerator for Real-Time Image Feature Extraction. IEEE Transactions on Circuits and Systems for Video Technology 22, 3 (March 2012), 340--351. https://doi.org/10.1109/TCSVT.2011.2162760 Google ScholarDigital Library
- D. Jeon, M. B. Henry, Y. Kim, I. Lee, Z. Zhang, D. Blaauw, and D. Sylvester. 2014. An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS. IEEE Journal of Solid-State Circuits 49, 5 (May 2014), 1271--1284. https://doi.org/10.1109/JSSC.2014.2309692 Google ScholarCross Ref
- Guangli Jiang, Leibo Liu, Wenping Zhu, Shouyi Yin, and Shaojun Wei. 2015. A 127 Fps in Full Hd Accelerator Based on Optimized AKAZE with Efficiency and Effectiveness for Image Feature Extraction. In Proceedings of the 52Nd Annual Design Automation Conference (DAC '15). ACM, New York, NY, USA, Article 87, 6 pages. https://doi.org/10.1145/2744769.2744772 Google ScholarDigital Library
- K. J. Lee K. Y., Byun. 2013. A hardware design of optimized orb algorithm with reduced hardware cost. Advanced Science and Technology Letters 43 (Dec 2013), 58--62. https://doi.org/10.1023/B:VISI.0000029664.99615.94Google ScholarDigital Library
- S. Leutenegger, M. Chli, and R. Y. Siegwart. 2011. BRISK: Binary Robust invariant scalable keypoints. In 2011 International Conference on Computer Vision. 2548--2555. https://doi.org/10.1109/ICCV.2011.6126542 Google ScholarDigital Library
- David G. Lowe. 2004. Distinctive Image Features from Scale-Invariant Keypoints. International Journal of Computer Vision 60, 2 (01 Nov 2004), 91--110. https://doi.org/10.1023/B:VISI.0000029664.99615.94 Google ScholarDigital Library
- B.S. Manjunath, C. Shekhar, and R. Chellappa. 1996. A new approach to image feature detection with applications. Pattern Recognition 29, 4 (1996), 627--640. https://doi.org/10.1016/0031-3203(95)00115-8 Google ScholarCross Ref
- Yong-Jin Na, Eun-Soo; Jeong. 2013. FPGA Implementation of SURF-based Feature extraction and Descriptor generation. Journal of Korea Multimedia Society 16, 4 (2013), 483--492. https://doi.org/10.9717/kmms.2013.16.4.483 Google ScholarCross Ref
- Adrien Bartoli Pablo Alcantarilla (Georgia Institute of Technolog), Jesus Nuevo (TrueVision Solutions AU). 2013. Fast Explicit Diffusion for Accelerated Features in Nonlinear Scale Spaces. In Proceedings of the British Machine Vision Conference. BMVA Press.Google Scholar
- J. Rettkowski, A. Boutros, and D. Göhringer. 2015. Real-time pedestrian detection on a xilinx zynq using the HOG algorithm. In 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). 1--8. https://doi.org/10.1109/ReConFig.2015.7393339 Google ScholarCross Ref
- E. Rosten and T. Drummond. 2005. Fusing points and lines for high performance tracking. In Tenth IEEE International Conference on Computer Vision (ICCV'05) Volume 1, Vol. 2. 1508--1515 Vol. 2. https://doi.org/10.1109/ICCV.2005.104 Google ScholarDigital Library
- E. Rublee, V. Rabaud, K. Konolige, and G. Bradski. 2011. ORB: An efficient alternative to SIFT or SURF. In 2011 International Conference on Computer Vision. 2564--2571. https://doi.org/10.1109/ICCV.2011.6126544 Google ScholarDigital Library
Index Terms
- Accelerated Embedded AKAZE Feature Detection Algorithm on FPGA
Recommendations
Designing Run-Time Reconfigurable Systems with JHDL
Run-time reconfigurable (RTR) systems are FPGA-based systems that reconfigure FPGAs during execution to alter hardware organization and composition to meet the varying needs of applications as they execute. These systems are difficult to describe with ...
FABulous: An Embedded FPGA Framework
FPGA '21: The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysAt the end of CMOS-scaling, the role of architecture design is increasingly gaining importance. Supporting this trend, customizable embedded FPGAs are an ingredient in ASIC architectures to provide the advantages of reconfigurable hardware exactly where ...
FPGA-based accelerator for object detection: a comprehensive survey
AbstractObject detection is one of the most challenging tasks in computer vision. With the advances in semiconductor devices and chip technology, hardware accelerators have been widely used. Field-programmable gate arrays (FPGAs) are a highly flexible ...
Comments