skip to main content
10.1145/3120895.3120920acmotherconferencesArticle/Chapter ViewAbstractPublication PagesheartConference Proceedingsconference-collections
research-article

Access Network Generation for Efficient Debugging of FPGAs

Published:07 June 2017Publication History

ABSTRACT

The inclusion of access networks in modern FPGAs can provide a large number of use cases notably in debugging. Using access networks can eliminate the need for frequent synthesis during the debugging phase, which results in saving debugging time and reducing the time to market. Using supervisory control by a processor, required networks can be configured just by minor software modification. Furthermore, connecting thousands of nodes to the debugging system is also a complicated issue. Utilizing IP-XACT files for automatic network generation can solve such problems. A Tcl file can then be used which can perform automatic network generation. This paper demonstrates an access network design, which requires only small resources and hence is suitable for large designs along with a framework for automatic connectivity generation.

References

  1. E. Hung and S.J.E. Wilton. "Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers." In Proc of the ACM/SIGDA international symposium on Field programmable gate arrays. ACM, 2013. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. Asaad, S., Bellofatto, R., Brezzo, B., Haymes, C., Kapur, M., Parker, B., Roewer, T., Saha, P., Takken, T. and Tierno, J., 2012, February. A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation. In Proc. of the ACM/SIGDA international symposium on Field Programmable Gate Arrays. ACM, 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. A. Herrmann and G. Nugent. "Embedded logic analyzer for a programmable logic device." U.S. Patent No. 6,389,558. 14 May 2002.Google ScholarGoogle Scholar
  4. H. Kuijsten. "Method and apparatus for a trace buffer in an emulation system." U.S. Patent No. 5,680,583. 21 Oct. 1997.Google ScholarGoogle Scholar
  5. Quinton, Bradley R., and Steven JE Wilton. "Concentrator access networks for programmable logic cores on SoCs." In Proc. of the Int. Symposium on Circuits and Systems (ISCAS), 2005.Google ScholarGoogle Scholar
  6. H.H. Khan and D. Göhringer. "FPGA Debugging by a Device Start and Stop Approach". In Proc. of the Int. Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE, 2016.Google ScholarGoogle Scholar
  7. T. Wheeler, P. Graham, B. Nelson, and B. Hutchings. "Using design-level scan to improve FPGA design bservability and controllability for functional verification." In Proc. of the Int. Conference on Field Programmable Logic and Applications (FPL). IEEE, 2001. Google ScholarGoogle ScholarCross RefCross Ref
  8. E. Hung and S.J.E. Wilton. "Limitations of incremental signal-tracing for FPGA debug." In Proc. of 22nd Int. Conference on Field Programmable Logic and Applications (FPL). IEEE, 2012. Google ScholarGoogle ScholarCross RefCross Ref
  9. Raghunathan, Vijay, Mani B. Srivastava, and Rajesh K. Gupta. "A survey of techniques for energy efficient on-chip communication." In Proc. of the 40th annual Design Automation Conference. ACM, 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Hwang, Frank. "The mathematical theory of nonblocking switching networks". Vol. 15. World Scientific, 2004. Google ScholarGoogle ScholarCross RefCross Ref
  11. Beneš, Václav E., ed. Mathematical theory of connecting networks and telephone traffic. Vol. 17. Academic press, 1965. Google ScholarGoogle ScholarCross RefCross Ref
  12. Pinsker, Mark S. "On the complexity of a concentrator." 7th International Telegraphic Conference. Vol. 4. 1973.Google ScholarGoogle Scholar
  13. Chung, F. R. K. "On concentrators, superconcentrators, generalizers, and nonblocking networks." The Bell System Technical Journal 58.8 (1979): 1765--1777. Google ScholarGoogle ScholarCross RefCross Ref
  14. Panjkov, Z., Wasserbauer, A., Ostermann, T., and Hagelauer, R. "Hybrid FPGA debug approach". In Proc. of the Int. Conference on Field Programmable Logic and Applications (FPL). IEEE, 2015. Google ScholarGoogle ScholarCross RefCross Ref
  15. IP-XACT Recommended Vendor Extensions to IEEE 1685-2014 (IP-XACT)Google ScholarGoogle Scholar
  16. B. R. Quinton, S. J. E. Wilton. "Post-Silicon Debug Using Programmable Logic Cores". Field-Programmable Technology, 45--48, 2005Google ScholarGoogle Scholar
  17. Narasimha, Madihally J. "A recursive concentrator structure with applications to self-routing switching networks." IEEE transactions on communications 42.234, (1994).Google ScholarGoogle Scholar
  18. Battaline, Robert P., et al. "Performance monitoring through JTAG 1149.1 interface." U.S. Patent No. 5,768,152. 16 Jun. 1998.Google ScholarGoogle Scholar
  19. Grimm, T., Lettnin, D., and Hübner, M. "Automatic generation of RTL connectivity checkers from SystemC TLM and IP-XACT descriptions". In Proc. of Nordic Circuits and Systems Conference (NORCAS). IEEE, 2016. Google ScholarGoogle ScholarCross RefCross Ref
  20. V. Berman, "Standards: The P1685 IP-XACT IP Metadata Standard," IEEE Design & Test of Computers, vol. 23, no. 4, pp. 316--317, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows, Std. IEEE Std. 1685--2009, 2010.Google ScholarGoogle Scholar
  22. J.-F. Le Tallec, et al., "Combining SystemC, IP-XACT and UML/MARTE in model-based SoC design". Workshop on Model Based Engineering for Embedded Systems Design (M-BED 2011), Grenoble, France, 2011, pp. 1--6.Google ScholarGoogle Scholar

Index Terms

  1. Access Network Generation for Efficient Debugging of FPGAs

    Recommendations

    Comments

    Login options

    Check if you have access through your login credentials or your institution to get full access on this article.

    Sign in
    • Published in

      cover image ACM Other conferences
      HEART '17: Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies
      June 2017
      172 pages
      ISBN:9781450353168
      DOI:10.1145/3120895

      Copyright © 2017 ACM

      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 7 June 2017

      Permissions

      Request permissions about this article.

      Request Permissions

      Check for updates

      Qualifiers

      • research-article
      • Research
      • Refereed limited

      Acceptance Rates

      Overall Acceptance Rate22of50submissions,44%

    PDF Format

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader