ABSTRACT
REDEFINE is a distributed dynamic dataflow architecture, designed for exploiting parallelism at various granularities as an embedded system-on-chip (SoC). This paper dwells on the flexibility of REDEFINE architecture and its execution model in accelerating real-time applications coupled with a WCET analyzer that computes execution time bounds of real time applications.
- Mythri et. al. Alle. 2009. REDEFINE: Runtime Reconfigurable Polymorphic ASIC. ACM Trans. Embed. Comput. Syst. 9, 2, Article 11 (Oct. 2009), 48 pages. Google ScholarDigital Library
- Jakob Engblom. 2002. Processor Pipelines and Static Worst-Case Execution Time Analysis. (2002).Google Scholar
- Paul Lokuciejewski and Peter Marwedel. 2011. Worst-case execution time aware compilation techniques for real-time systems. Springer, Dordrecht, Heidelberg, New York. 3--5 pages. Google ScholarCross Ref
Recommendations
Quality of service capabilities for hard real-time applications on multi-core processors
RTNS '13: Proceedings of the 21st International conference on Real-Time Networks and SystemsComputing Worst-Case Execution Times (WCETs) for applications executed on multi-core processors is a challenging topic since possible interferences on shared resources need to be considered. Some approaches are already proposed in literature, but the ...
parMERASA -- Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability
DSD '13: Proceedings of the 2013 Euromicro Conference on Digital System DesignEngineers who design hard real-time embedded systems express a need for several times the performance available today while keeping safety as major criterion. A breakthrough in performance is expected by parallelizing hard real-time applications and ...
Monitoring and WCET analysis in COTS multi-core-SoC-based mixed-criticality systems
DATE '14: Proceedings of the conference on Design, Automation & Test in EuropeThe performance and power efficiency of multi-core processors are attractive features for safety-critical applications, for example in avionics. But the inherent use of shared resources complicates timing analysability. In this paper we discuss a novel ...
Comments