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REDEFINE®™: a case for WCET-friendly hardware accelerators for real time applications (work-in-progress)

Published:15 October 2017Publication History

ABSTRACT

REDEFINE is a distributed dynamic dataflow architecture, designed for exploiting parallelism at various granularities as an embedded system-on-chip (SoC). This paper dwells on the flexibility of REDEFINE architecture and its execution model in accelerating real-time applications coupled with a WCET analyzer that computes execution time bounds of real time applications.

References

  1. Mythri et. al. Alle. 2009. REDEFINE: Runtime Reconfigurable Polymorphic ASIC. ACM Trans. Embed. Comput. Syst. 9, 2, Article 11 (Oct. 2009), 48 pages. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. Jakob Engblom. 2002. Processor Pipelines and Static Worst-Case Execution Time Analysis. (2002).Google ScholarGoogle Scholar
  3. Paul Lokuciejewski and Peter Marwedel. 2011. Worst-case execution time aware compilation techniques for real-time systems. Springer, Dordrecht, Heidelberg, New York. 3--5 pages. Google ScholarGoogle ScholarCross RefCross Ref

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  • Published in

    cover image ACM Other conferences
    CASES '17: Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion
    October 2017
    51 pages
    ISBN:9781450351843
    DOI:10.1145/3125501

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    • Published: 15 October 2017

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